AD9958SLASHPCB datasheet(23/40 Pages) AD

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AD9958

Rev. 0 | Page 23 of 40

The AD9958 has the ability to ramp up or ramp down (RU/RD)

the output amplitude (using the 10-bit output scalar) before and

after a linear sweep. If the RU/RD feature is desired, unused

profile pins or unused SDIO_1:3 pins can be configured for the

RU/RD operation.

To enable linear sweep mode for a particular channel, AFP bits

(CFR <23:22>), modulation level bits (FR1 <9:8>), and the

linear sweep enable bit (CFR <14>) are programmed. The AFP

bits determine the type of linear sweep to be performed. The

modulation level bits must be set to 00 (2-level) for that specific

channel (see Table 19 and Table 20).

Table 19.

AFP

CFR <23:22>

Linear Sweep Enable

CFR <14>

Description

N/A

Amplitude sweep

Frequency sweep

Phase sweep

Table 20.

Modulation Level Bits FR1 <9:8>

Description

2-level modulation

4-level modulation

8-level modulation

16-level modulation

Setting the Slope of the Linear Sweep

The slope of the linear sweep is set by the intermediate step size

(delta-tuning word) between S0 and E0 and the time spent

(sweep ramp rate word) at each step. The resolution of the

delta-tuning word is 32 bits for frequency, 14 bits for phase, and

10 bits for amplitude. The resolution for the delta ramp rate

word is 8 bits.

In linear sweep, each channel is assigned a rising delta word

(RDW, Register 0x08) and a rising sweep ramp rate word

(RSRR, Register 0x07). These settings apply when sweeping up

towards E0. The falling delta word (FDW, Register 0x09) and

falling sweep ramp rate (FSRR, Register 0x07) apply when

sweeping down towards S0.

Note the sweep accumulator overflows if the rising or falling

delta word is too large. To prevent this from happening, the

magnitude of the rising or falling delta word should not be

greater than the difference between full scale and the E0 value

(full scale − E0). For a frequency sweep, full scale is 231−1. For

a phase sweep, full scale is 214 −1. For an amplitude sweep, full

scale is 210−1.

The following graph displays a linear sweep up and then down

using a profile pin. Note that the no-dwell bit is disabled; other-

wise, the sweep accumulator returns to 0 upon reaching EO.

RDW

RSRR

FSRR

∆f,p,a

FDW

TIME

PROFILE PIN

∆f,p,a

∆t

Figure 35.

For a piecemeal or a nonlinear transition between S0 and E0,

the delta-tuning words and ramp rate words can be repro-

grammed during the transition to produce the desired response.

The formulae for calculating the step size of RDW or FDW for

delta frequency, delta phase, or delta amplitude are as follows:

CLK

SYNC

RDW

⎟

⎠

⎞

⎜

⎝

⎛

∆

(Hz)

⎟

⎠

⎞

⎜

⎝

⎛

360

RDW

ΔΦ

1024

⎟

⎠

⎞

⎜

⎝

⎛

∆

RDW

(DAC full-scale current)

The formula for calculating delta time from RSRR or FSRR is

CLK

SYNC

RSRR

⎟

⎠

⎞

⎜

⎝

⎛

At 500 MSPS operation (SYNC_CLK =125 MHz), the maxi-

mum time interval between steps is 1/125 MHz × 256 = 2.048 µs.

The minimum time interval is (1/125 MHz) × 1 = 8.0 ns.

The sweep ramp rate block (timer) consists of a loadable 8-bit

down counter that continuously counts down from the loaded

value to 1. When the ramp rate timer equals 1, the proper ramp

rate value is loaded and the counter begins counting down to 1

again. This load and count down operation continues for as

long as the timer is enabled. However the count can be reloaded

before reaching 1 by either of the following two methods.

Method one is by changing the profile pin. When the profile pin

changes from Logic 0 to Logic 1, the rising sweep ramp rate

then proceeds to count down as normal. When the profile pin

changes from Logic 1 to Logic 0, the falling sweep ramp rate

then proceeds to count down as normal.

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