CS5530A datasheet(14/259 Pages) NSC

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Revision 1.1

Signal Definitions (Continued)

2.1

PIN ASSIGNMENTS

The tables in this section use several common abbrevia-

tions. Table 2-1 lists the mnemonics and their meanings.

Figure 2-2 shows the pin assignment for the CS5530A with

Tables 2-2 and 2-3 listing the pin assignments sorted by pin

number and alphabetically by signal name, respectively.

In Section 2.2 "Signal Descriptions" on page 23 a descrip-

tion of each signal within its associated functional group is

provided.

In the signal definitions, references to F0-F4, F1BAR,

F2BAR, F3BAR, F4BAR, and PCIUSB are made. These

terms relate to designated register spaces. Refer to

Table 4-1 "PCI Configuration Address Register (0CF8h)"

on page 141 for details regarding these register spaces

and their access mechanisms.

Table 2-1. Pin Type Definitions

Mnemonic

Definition

Input pin1

All buffers are 5 volt tolerant.

I/O

Bidirectional pin1,2

All digital bidirectional and output pins can be TRI-

STATE signals unless a weak pull-up is enabled.

Output pin1, 2

Open-drain output structure that

allows multiple devices to share the

pin in a wired-OR configuration

Pull-up resistor

SMT

Schmitt Trigger

VDD (PWR)

Power pin

VSS (GND)

Ground pin

The “#” symbol at the end of a signal

name indicates that the active, or

asserted state occurs when the signal

is at a low voltage level. When “#” is

not present after the signal name, the

signal is asserted when at a high volt-

age level.

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