CS5530A datasheet(45/259 Pages) NSC

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Functional Description (Continued)

3.1.2

PSERIAL Pin Interface

The majority of the system power management logic is

implemented in the CS5530A, but a minimal amount of

logic is contained within the GX-series processor to provide

information that is not externally visible (e.g., graphics con-

troller).

The processor implements a simple serial communications

mechanism to transmit the CPU status to the CS5530A.

The processor accumulates CPU events in an 8-bit register

(defined in Table 3-1) which it transmits serially every 1 to

10 µs.

The packet transmitter holds the serial output pin (PSE-

RIAL) low until the transmission interval timer has elapsed.

Once the timer has elapsed, the PSERIAL pin is held high

for two clocks to indicate the start of packet transmission.

The contents of the Serial Packet Register are then shifted

out starting from bit 7 down to bit 0. The PSERIAL pin is

held high for one clock to indicate the end of packet trans-

mission and then remains low until the next transmission

interval. After the packet transmission is complete, the pro-

cessor’s Serial Packet Register’s contents are cleared.

The processor’s input clock is used as the clock reference

for the serial packet transmitter.

Once a bit in the register is set, it remains set until the com-

pletion of the next packet transmission. Successive events

of the same type that occur between packet transmissions

are ignored. Multiple unique events between packet trans-

missions accumulate in this register. The processor trans-

mits the contents of the serial packet only when a bit in the

Serial Packet Register is set and the interval timer has

elapsed.

For more information on the Serial Packet Register refer-

enced in Table 3-1, refer to the appropriate GX-series pro-

cessor data book.

The CS5530A decodes the serial packet after each trans-

mission and performs the power management tasks

relatedtovideo retrace.

3.1.2.1

Video Retrace Interrupt

Bit7 of the “Serial Packet” canbeused to generateanSMI

whenever a video retrace occurs within the processor. This

function is normally not used for power management but for

SoftVGA routines.

Setting F0 Index 83h[2] = 1 (bit details on page 163)

enables this function. A read only status register located at

F1BAR+Memory Offset 00h[5] (bit details on page 183)

can beread tosee if theSMI wascausedby a video

retrace event.

Table 3-1. GX-Series Processor Serial Packet

Bit

Description

Video IRQ: This bit indicates the occurrence of a video

vertical sync pulse. This bit is set at the same time that

the VINT (Vertical Interrupt) bit gets set in the

DC_TIMING_CFG register. The VINT bit has a corre-

sponding enable bit (VIEN) in the DC_TIM_CFG regis-

ter.

CPU Activity: This bit indicates the occurrence of a

level 1 cache miss that was not a result of an instruc-

tion fetch. This bit has a corresponding enable bit in

the PM_CNTL_TEN register.

5:2

Reserved

Programmable Address Decode: This bit indicates

the occurrence of a programmable memory address

decode. The bit is set based on the values of the

PM_BASE register and the PM_MASK register. The

PM_BASE register can be initialized to any address in

the full CPU address range.

Video Decode: This bit indicates that the CPU has

accessed either the display controller registers or the

graphics memory region. This bit has a corresponding

enable bit in the PM_CNTRL_TEN.

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