CS5530A datasheet(56/259 Pages) NSC

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Revision 1.1

Functional Description (Continued)

3.4.1.2

Active Idle

This state is the most powerful power management state

because it is an operational state. The CPU has executed a

HLT instruction and has asserted the SUSPA# signal. The

operating system has control of the entry of this state

because the OS has either executed the HLT or made a

BIOS call to indicate idle, and the BIOS executed the HLT

instruction. The display refresh subsystem is still active but

the CPU is not executing code. The clock is stopped to the

processing core in this state and considerable power is

saved in the processor. The CS5530A takes advantage of

this power state by stopping the clock to some of the inter-

nal circuitry. This power saving mode can be enabled/dis-

abled by programming F0 Index 96h[4] (see Table 3-12).

The CS5530A can still make bus master requests for IDE,

audio, USB, and ISA from this state. When the CS5530A or

any other device on the PCI bus asserts REQ#, the CPU

deassertsSUSPA#for thedurationofREQ#activity. Once

REQ# has gone inactive and all PCI cycles have stopped,

the CPU reasserts SUSPA#. SUSPA# remains active until

the CPU receives an INTR or SMI event which ends the

CPU halt condition.

3.4.1.3

Suspend

This state is similar to the Active Idle state except that the

CPU enters this state because the CS5530A asserted

SUSP#. The CS5530A deasserts SUSP# when an INTR or

SMI event occurs. The Suspend Configuration register is

shown in Table 3-12, however, also see the tables listed

below for a more complete understanding on configuring

the Suspend state.

• F0 Index BCh in Table 3-13 "Clock Stop Control

• Related registers in Table 3-14 "Suspend Modulation

Related Registers" on page 59.

• F0 Index AEh in Table 3-16 "APM Support Registers" on

page 62.

Table 3-12. Suspend Configuration Register

Bit

Description

F0 Index 96h

Suspend Configuration Register (R/W)

Reset Value = 00h

7:5

Reserved: Set to 0.

Power Savings Mode: 0 = Enable; 1 = Disable.

Include ISA Clock in Power Savings Mode: 0 = ISA clock not included; 1 = ISA clock included.

Suspend Mode Configuration: “Special 3 Volt Suspend” mode to support powering down a GX-series processor during

Suspend. 0 = Disable; 1 = Enable.

SMI Speedup Configuration: Selects how Suspend Modulation function reacts when an SMI occurs.

0 = Use the IRQ Speedup Timer Count Register (F0 Index 8Ch) to temporarily disable Suspend Modulation when an SMI

occurs.

1 = Disable Suspend Modulation when an SMI occurs until a read to the SMI Speedup Disable Register (F1BAR+Memory

Offset 08h).

The purpose of this bit is to disable Suspend Modulation while the CPU is in the System Management Mode so that VSA

technology and power management operations occur at full speed. Two methods for accomplishing this are either to map

the SMI into the IRQ Speedup Timer Count Register (F0 Index 8Ch), or to have the SMI disable Suspend Modulation until

the SMI handler reads the SMI Speedup Disable Register (F1BAR+Memory Offset 08h). The latter is the preferred method.

The IRQ speedup method is provided for software compatibility with earlier revisions of the CS5530A. This bit has no effect

if the Suspend Modulation feature is disabled (bit 0 = 0).

Suspend Modulation Feature: 0 = Disable; 1 = Enable.

When enabled, the SUSP# pin will be asserted and deasserted for the durations programmed in the Suspend Modulation

OFF/ON Count Registers (F0 Index 94h/95h).

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