CS5530A datasheet(62/259 Pages) NSC

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Functional Description (Continued)

3.4.2

APM Support

Some IA systems rely solely on an APM (Advanced Power

Management) driver for enabling the operating system to

power-manage the CPU. APM provides several services

which enhance the system power management and is the-

oretically the best approach; but in its current form, APM is

imperfect for the following reasons:

• APM is an OS-specific driver, and may not be available

for some operating systems.

• Application support is inconsistent. Some applications in

foreground may prevent Idle calls.

• APM does not help with Suspend determination or

peripheral power management.

The CS5530A provides two entry points for APM support:

• Software CPU Suspend control via the CPU Suspend

Command Register (F0 Index AEh)

• Software SMI entry via the Software SMI Register (F0

Index D0h). This allows the APM BIOS to be part of the

SMI handler.

These registers are shown in Table 3-16.

Table 3-16. APM Support Registers

Bit

Description

F0 Index AEh

CPU Suspend Command Register (WO)

Reset Value = 00h

7:0

Software CPU Suspend Command (Write Only): If bit 0 in the Clock Stop Control Register is set low (F0 Index BCh[0] =

0) and all SMI status bits are 0, a write to this register causes a SUSP#/SUSPA# handshake with the CPU, placing the CPU

in a low-power state. The data written is irrelevant. Once in this state, any unmasked IRQ or SMI releases the CPU halt con-

dition.

If F0 Index BCh[0] = 1, writing to this register invokes a full system Suspend. In this case, the SUSP_3V pin is asserted after

the SUSP#/SUSPA# halt. Upon a Resume event (see Note), the PLL delay programmed in the F0 Index BCh[7:4] is invoked,

allowing the clock chip and CPU PLL to stabilize before deasserting the SUSP# pin.

Note: If the clocks are stopped, the external IRQ4 and IRQ3 pins, when enabled (F3BAR+Memory Offset 1Ah[4:3]), are the

only IRQ pins that can be used as a Resume event. If GPIO2, GPIO1, and GPIO0 are enabled as an external SMI

source (F0 Index 92h[2:0]), they too can be used as a Resume event. No other CS5530A pins can be used to wake-

up the system from Suspend when the clocks are stopped. As long as the 32 KHz clock remains active, internal SMI

events are also Resume events.

F0 Index D0h

Software SMI Register (WO)

Reset Value = 00h

7:0

Software SMI (Write Only): A write to this location generates an SMI. The data written is irrelevant. This register allows

software entry into SMM via normal bus access instructions.

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