CS5530A datasheet(37/259 Pages) NSC

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Signal Definitions (Continued)

FP_DATA[15:0]/

SA[15:0]

Refer

Table

2-3

Limited ISA Mode: Flat Panel Data Port Lines 15 through 0

This is the data port to an attached active matrix TFT panel. This port may

optionally be tied to a DSTN formatter chip, LVDS transmitter, or digital

NTSC/PAL encoder.

F4BAR+Memory Offset 04h[7] enables the flat panel data bus:

0 = FP_DATA[17:0] is forced low

1 = FP_DATA[17:0] is driven based upon power sequence control

I/O

ISA Master Mode: System Address Bus Lines 15 through 0

These pins function as SA[15:0] and the pins designated as SA/SD[15:0]

function only as SD[15:0].

Note that SA[19:16] are dedicated address pins and GPIO[7:4] function as

SA[23:20] only.

FP_CLK

Limited ISA Mode: Flat Panel Clock

This is the clock for the flat panel interface.

ISA Master Mode: No Function

In the ISA Master mode of operation, the CS5530A cannot support TFT flat

panels or TV controllers.

FP_CLK_EVEN

Limited ISA Mode: Flat Panel Even Clock

This is an optional output clock for a set of external latches used to de-multi-

plex the flat panel data bus into two channels (odd/even). Typically this

would be used to interface to a pair of LVDS transmitters driving an XGA

resolution flat panel.

F4BAR+Memory Offset 04h[12] enables the FP_CLK_EVEN output:

0 = Standard flat panel

1 = XGA flat panel

ISA Master Mode: No Function

In the ISA Master mode of operation, the CS5530A can not support TFT flat

panels or TV controllers.

FP_HSYNC

Limited ISA Mode: Flat Panel Horizontal Sync Input

This is the horizontal sync input reference from the processor’s display con-

troller. The timing of this signal is independent of the standard (CRT) hori-

zontal sync input to allow a different timing relationship between the flat

panel and an attached CRT.

ISA Master Mode: No Function

In the ISA Master mode of operation, the CS5530A can not support TFT flat

panels or TV controllers.

FP_HSYNC_OUT

/SMEMW#

Limited ISA Mode: Flat Panel Horizontal Sync Output

This is the horizontal sync for an attached active matrix TFT flat panel. This

represents a delayed version of the input flat panel horizontal sync signal

with the appropriate pipeline delay relative to the pixel data.

ISA Master Mode: System Memory Write

Refer to Section 2.2.5 "ISA Bus Interface" on page 28 for this signal’s defini-

tion.

2.2.11 Display Interface (Continued)

Signal Name

No.

Type

Description

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