CS5530A datasheet(59/259 Pages) NSC

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Functional Description (Continued)

Table 3-14. Suspend Modulation Related Registers

Bit

Description

F0 Index 80h

Power Management Enable Register 1 (R/W)

Reset Value = 00h

Video Speedup: Any video activity, as decoded from the serial connection (PSERIAL register, bit 0) from the GX-series pro-

cessor disables clock throttling (via SUSP#/SUSPA# handshake) for a configurable duration when the system is power man-

aged using CPU Suspend modulation. 0 = Disable; 1 = Enable.

The duration of the speedup is configured in the Video Speedup Timer Count Register (F0 Index 8Dh). Detection of an

external VGA access (3Bxh, 3Cxh, 3Dxh and A000h-B7FFh) on the PCI bus is also supported. This configuration is non-

standard, but it does allow the power management routines to support an external VGA chip.

IRQ Speedup: Any unmasked IRQ (per I/O Port 021h/0A1h) or SMI disables clock throttling (via SUSP#/SUSPA# hand-

shake) for a configurable duration when the system is power managed using CPU Suspend modulation.

0 = Disable; 1 = Enable.

The duration of the speedup is configured in the IRQ Speedup Timer Count Register (F0 Index 8Ch).

F0 Index 8Ch

IRQ Speedup Timer Count Register (R/W)

Reset Value = 00h

7:0

IRQ Speedup Timer Count: This register holds the load value for the IRQ speedup timer. It is loaded into the timer when

Suspend Modulation is enabled (F0 Index 96h[0] = 1) and an INTR or an access to I/O Port 061h occurs. When the event

occurs, the Suspend Modulation logic is inhibited, permitting full performance operation of the CPU. Upon expiration, no SMI

is generated; the Suspend Modulation begins again. The IRQ speedup timer’s timebase is 1 ms.

This speedup mechanism allows instantaneous response to system interrupts for full-speed interrupt processing. A typical

value here would be 2 to 4 ms.

F0 Index 8Dh

Video Speedup Timer Count Register (R/W)

Reset Value = 00h

7:0

Video Speedup Timer Count: This register holds the load value for the Video speedup timer. It is loaded into the timer

when Suspend Modulation is enabled (F0 Index 96h[0] = 1) and any access to the graphics controller occurs. When a video

access occurs, the Suspend Modulation logic is inhibited, permitting full-performance operation of the CPU. Upon expira-

tion, no SMI is generated; the Suspend Modulation begins again. The video speedup timer’s timebase is 1 ms.

This speedup mechanism allows instantaneous response to video activity for full speed during video processing calcula-

tions. A typical value here would be 50 to 100 ms.

Index 94h

Suspend Modulation OFF Count Register (R/W)

Reset Value = 00h

7:0

Suspend Signal Deasserted Count: This 8-bit value represents the number of 32 µs intervals that the SUSP# pin will be

deasserted to the GX-series processor. This timer, together with the Suspend Modulation ON Count Register (F0 Index

95h), perform the Suspend Modulation function for CPU power management. The ratio of the on-to-off count sets up an

effective (emulated) clock frequency, allowing the power manager to reduce CPU power consumption.

This timer is prematurely reset if an enabled speedup event occurs. The speedup events are IRQ speedups and video

speedups.

Index 95h

Suspend Modulation ON Count Register (R/W)

Reset Value = 00h

7:0

Suspend Signal Asserted Count: This 8-bit value represents the number of 32 µs intervals that the SUSP# pin will be

asserted. This timer, together with the Suspend Modulation OFF Count Register (F0 Index 94h), perform the Suspend Mod-

ulation function for CPU power management. The ratio of the on-to-off count sets up an effective (emulated) clock fre-

quency, allowing the power manager to reduce CPU power consumption.

This timer is prematurely reset if an enabled speedup event occurs. The speedup events are IRQ speedups and video

speedups.

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