CS5530A datasheet(42/259 Pages) NSC

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Revision 1.1

Functional Description (Continued)

3.1

PROCESSOR INTERFACE

The CS5530A interface to a GX-series processor consists

of seven miscellaneous connections, the PCI bus interface

signals, plus the display controller connections. Figure 3-1

shows the interface requirements. Note that the PC/AT leg-

acy pins NMI, WM_RST, and A20M are all virtual functions

executed in SMM (System Management Mode) by the

BIOS.

• PSERIAL is a one-way serial bus from the processor to

the CS5530A used to communicate power management

states and VSYNC information for VGA emulation.

• IRQ13 is an input from the processor indicating that a

floating point error was detected and that INTR should

be asserted.

• INTR is the level output from the integrated 8259 PICs

and is asserted if an unmasked interrupt request (IRQn)

is sampled active.

• SMI# is a level-sensitive interrupt to the processor that

can be configured to assert on a number of different

system events. After an SMI# assertion, SMM is entered

and program execution begins at the base of the SMM

address space. Once asserted, SMI# remains active

until the SMI source is cleared.

• SUSP# and SUSPA# are handshake pins for imple-

menting CPU Clock Stop and clock throttling.

• CPU_RST resets the CPU and is asserted for approxi-

mately 9 ms after the negation of POR#.

• PCI bus interface signals.

• Display subsystem interface connections.

Figure 3-1. Processor Signal Connections

SERIALP

IRQ13

SMI#

INTR

SUSP#

SUSPA#

AD[31:0]

C/BE[3:0]#

PAR

FRAME#

IRDY#

TRDY#

STOP#

LOCK#

DEVSEL#

PERR#

SERR#

REQ0#

PSERIAL

IRQ13

SMI#

CPU_RST

INTR

SUSP#

SUSPA#

AD[31:0]

C/BE[3:0]#

PAR

FRAME#

IRDY#

TRDY#

STOP#

LOCK#

DEVSEL#

PERR#

SERR#

REQ#

GNT#

GNT0#

Geode™ GX-Series

Geode™ CS5530A

RESET

PCLK

CRT_HSYNC

CRT_VSYNC

PIXEL[17:0]

FP_HSYNC

FP_VSYNC

ENA_DISP

VID_VAL

VID_CLK

VID_DATA[7:0]

VID_RDY

PCLK

HSYNC

VSYNC

PIXEL[23:0]

FP_HSYNC

FP_VSYNC

ENA_DISP

VID_VAL

VID_CLK

VID_DATA[7:0]

VID_RDY

DCLK

I/O Companion

Processor

Note:

Refer to Figure 3-3 on page 44 for correct

interconnection of PIXEL lines with the processor.

Note

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