CS5530A datasheet(24/259 Pages) NSC

24 / 259 page

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Revision 1.1

Signal Definitions (Continued)

2.2.3

CPU Interface

Signal Name

No.

Type

Description

INTR

P26

Strap

Option

CPU Interrupt Request

INTR is the level output from the integrated 8259 PICs and is asserted if an

unmasked interrupt request (IRQn) is sampled active.

StrapOptionSelect Pin

Pin P26 is a strap option select pin. It is used to select whether the

CS5530A operates in Limited ISA or ISA Master mode.

ISA Limited Mode—Strap pin P26 low through a 10-kohm resistor.

ISA Master Mode—Strap pin P26 high through a 10-kohm resistor.

SMI#

P25

I/O

System Management Interrupt

SMI# is a level-sensitive interrupt to the CPU that can be configured to

assert on a number of different system events. After an SMI# assertion,

System Management Mode (SMM) is entered, and program execution

begins at the base of SMM address space.

Once asserted, SMI# remains active until all SMI sources are cleared.

IRQ13

R23

IRQ13

IRQ13 is an input from the processor indicating that a floating point error

was detected and that INTR should be asserted.

PSERIAL

L26

Power Management Serial Interface

PSERIAL is the unidirectional serial data link between the GX-series pro-

cessor and the CS5530A. An 8-bit serial data packet carries status on power

management events within the CPU. Data is clocked synchronous to the

PCICLK input clock.

SUSP#

K26

CPU Suspend

SUSP# asserted requests that the CPU enters Suspend mode and the CPU

asserts SUSPA# after completion. The SUSP# pin is deasserted if SUSP#

has gone active and any Speedup or Resume event has occurred, including

expiration of the Suspend Modulation ON timer, which is loaded from F0

Index 95h. If the SUSP#/SUSPA# handshake is configured as a system 3

Volt Suspend, the deassertion of SUSP# is delayed by an interval pro-

grammed in F0 Index BCh[7:4] to allow the system clock chip and the pro-

cessor to stabilize.

The SUSP#/SUSPA# handshake occurs as a result of a write to the Sus-

pend Notebook Command Register (F0 Index AFh), or expiration of the Sus-

pend Modulation OFF timer (loaded from F0 Index 94h) when Suspend

Modulation is enabled. Suspend Modulation is enabled via F0 Index 96h[0].

If SUSPA# is asserted as a result of a HALT instruction, SUSP# does not

deassert when the Suspend Modulation ON timer (loaded from F0 Index

95h) expires.

SUSPA#

L25

CPU Suspend Acknowledge

SUSPA# is a level input from the processor. When asserted it indicates the

CPU is in Suspend mode as a result of SUSP# assertion or execution of a

HALT instruction.

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