CS5530A datasheet(79/259 Pages) NSC

79 / 259 page

Revision 1.1

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Functional Description (Continued)

Figure 3-7 shows an example SMI tree for checking and

clearing the source of general purpose timer and the user

defined trap generated SMIs.

Table 3-33 on page 80 shows the bit formats of the read to

clear Top Level SMI Status Register (F1BAR+Memory Off-

set02h). Table3-34startingonpage81shows the bit for-

mats of the read to clear second level SMI status registers.

For information regarding the location of the corresponding

mirror register, refer to the note in the footer of the register

description.

Keep in mind, all SMI sources in the CS5530A are reported

into the Top Level SMI Status Registers (F1BAR+Memory

Offset 00h/02h); however, this discussion is regarding

power management SMIs. For details regarding audio SMI

events/reporting, refer to Section 3.7.2.2 "Audio SMI

Related Registers" on page 123.

Figure 3-7. General Purpose Timer and UDEF Trap SMI Tree Example

SMI# Asserted

SMM software reads SMI Header

If Bit X = 0

(Internal SMI)

If Bit X = 1

(External SMI)

Call internal SMI handler

to take appropriate action

Geode™ CS5530A

F1BAR+Memory

Read to Clear

to determine

top-level source

of SMI

F1BAR+Memory

Offset 06h

Read to Clear

Bits [15:10]

Bits [8:0]

Bit 9

GTMR_TRP_SMI

Offset 02h

Geode™

to determine

second-level

source of SMI

Bit 5

PCI_TRP_SMI

Bit 4

UDEF3_TRP_SMI

Bit 3

UDEF2_TRP_SMI

Bit 2

UDEF1_TRP_SMI

Bit 1

GPT2_SMI

Bit 0

GPT1_SMI

Take

Appropriate

Action

Other_SMI

If bit 9 = 1,

Source of SMI

is GP Timer or UDEF Trap

Bits 15:6

RSVD

Top Level

Second Level

SMI Deasserted after all SMI Sources are Cleared

(i.e., Top and Second Levels - note some sources may have a Third Level)

GX-Series

Processor

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