SLG46110V datasheet(26/82 Pages) DIALOG

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000-0046110-106

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SLG46110

8.2 Matrix Output Table

Table 15. Matrix Output Table

Address

Matrix Output Signal Function

Matrix Output

Number

reg <4:0>

Pin 3 digital out source

reg <9:5>

Pin 4 digital out source

reg <14:10>

Pin 6 digital out source

reg <19:15>

Pin 6 output enable

reg <24:20>

in0 of LUT2_0 (Clock Input of DFF0)

reg <29:25>

in1 of LUT2_0 (Data Input of DFF0)

reg <34:30>

in0 of LUT2_1 (Clock Input of DFF1)

reg <39:35>

in1 of LUT2_1 (Data Input of DFF1)

reg <44:40>

in0 of LUT2_2

reg <49:45>

in1 of LUT2_2

reg <54:50>

in0 of LUT2_3

reg <59:55>

in1 of LUT2_3

reg <64:60>

in0 of LUT3_0 (Clock Input of DFF2 with nReset/nSet)

reg <69:65>

in1 of LUT3_0 (Data input of DFF2 with nReset/nSet)

reg <74:70>

in2 of LUT3_0 (Resetb or Setb of DFF2 with nReset/nSet)

reg <79:75>

in0 of LUT3_1 (Clock Input of DFF3 with nReset/nSet)

reg <84:80>

in1 of LUT3_1 (Data input of DFF3 with nReset/nSet)

reg <89:85>

in2 of LUT3_1 (Resetb or Setb of DFF3 with nReset/nSet)

reg <94:90>

in0 of LUT3_2

reg <99:95>

in1 of LUT3_2

reg <104:100>

in2 of LUT3_2

reg <109:105>

in0 of LUT3_3

reg <114:110>

in1 of LUT3_3

reg <119:115>

in2 of LUT3_3

reg <124:120>

in0 of LUT3_4 (Input of pipe delay)

reg <129:125>

in1 of LUT3_4 (Resetb of pipe delay)

reg <134:130>

in2 of LUT3_4 (Clock of pipe delay)

reg <139:135>

in0 of LUT4_0 (Input for Delay2 ext. clock or Counter2 external Clock)

reg <144:140>

in1 of LUT4_0 (Input for delay2 or counter2 reset input)

reg <149:145>

in2 of LUT4_0

reg <154:150>

in3 of LUT4_0

reg <159:155>

Input for delay0 or counter0 reset input

reg <164:160>

Input for delay1 or counter1 reset input

reg <169:165>

Input for Delay0/1 ext. clock or Counter1 external Clock

reg <174:170>

Input for delay3 or counter3 reset input

reg <179:175>

pdb for ACMP0

reg <184:180>

pdb for ACMP1

reg <189:185>

Input for programmable delay(deglitch filter input)37

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