SLG46110V datasheet(46/82 Pages) DIALOG

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000-0046110-106

Page 45 of 81

SLG46110

Each of the ACMP cells has a negative input signal that is either created from an internal VREF or provided by the external

reference/source. Internal Vref accuracy is optimized near 1000 mV selection.

Note: Power supply control options have influence on the ACMP operation.

Note: Any ACMP powered on enables the BandGap internal circuit as well. An analog voltage will appear on Vref (even when the

Force BandGap option is set as Disabled).

Analog comparators have the following configurable options:

•

Hysteresis: Input signal hysteresis options are Disable, 25 mV, 50 mV, 200 mV.

•

Low Bandwidth: Enable, Disable;

•

IN+ Gain: 1X, 0.5X, 0.33X, 0.25X;

•

IN+ source:

• ACMP0 IN+ options are PIN 3, VDD;

• ACMP1 IN+ options are PIN 6, ACMP0 IN+;

•IN- source:

• ACMP0 IN- options are 24 internal reference sources (50 mV – 1200 mV) and VDD/3, VDD/4, PIN 4;

• PWR UP=0 – ACMP is powered down; PWR UP=1 – ACMP is powered up.

All ACMPs can have a common negative input. This can be achieved by configuring ACMP0 PIN 4 analog I/O connection.

11.1 ACMP0 Block Diagram

Figure 20. ACMP0 Block Diagram

11010

11001-

00000

Internal

Vref

PIN4: ACMP0(-)

PIN3: ACMP0(+)

External VDD 1.71 V ~ 5.5 V

Selectable

Gain

reg <364:363>

to ACMP1 MUX input

Vref

From Connection

Matrix Output <12>

pdb

LBW

Selection

ibias

reg <365>

Hysteresis

Selection

reg <362:361>

L/S

ON after

100

s Delay

To Connection

Matrix Input<19>

reg <360:356>

*PIN3_aio_en; reg <366>

OFF after

s Delay

*PIN3_aio_en:

if reg <385:383> = ’011’ then 1, otherwise: 0

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