SLG46110V datasheet(57/82 Pages) DIALOG

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000-0046110-106

Page 56 of 81

SLG46110

12.1 CNT/DLY0 Register Settings

12.2 CNT/DLY1 Register Settings

Table 41. CNT/DLY0 Register Settings

Signal Function

Address

Counter/Delay0

Mode Select

reg <314>

0: Delay Mode

1: Counter Mode

Counter/Delay0

Clock Source Select

(external clock is

only for counter

mode)

reg <317:315>

000: Internal OSC Clock

001: OSC/4

010: OSC/12

011: OSC/24

100: OSC/64

101: External Clock

110: Reserved

111: Counter3 Overflow

Counter0 Control

Data/Delay0 Time

Control

reg <325:318>

1-256: (delay time = (counter control data +2) /freq)

Delay0 Mode Select

or asynchronous

counter reset

reg <327:326>

00: Delay on both falling and rising edges(for delay & counter reset)

01: Delay on falling edge only (for delay & counter reset)

10: Delay on rising edge only (for delay & counter reset)

11: No delay on either falling or rising edges / high level reset for counter mode

Table 42. CNT/DLY1 Register Settings

Signal Function

Address

Counter/Delay1

Mode Select

reg <328>

0: Delay Mode

1: Counter Mode

Counter/Delay1

Clock Source Select

(external clock is

only for counter

mode)

reg <331:329>

000: Internal OSC Clock

001: OSC/4

010: OSC/12

011: OSC/24

100: OSC/64

101: External Clock

110: Reserved

111: Counter0 Overflow

Counter1 Control

Data/Delay1 Time

Control

reg <339:332>

1-256: (delay time = (counter control data +2) /freq)

Delay1 Mode Select

or asynchronous

counter reset

reg <341:340>

00: Delay on both falling and rising edges(for delay & counter reset)

01: Delay on falling edge only (for delay & counter reset)

10: Delay on rising edge only (for delay & counter reset)

11: No delay on either falling or rising edges / high level reset for counter mode

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