SLG46110V datasheet(63/82 Pages) DIALOG

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SLG46110

15.0 Power On Rest (POR)

The SLG46110 has a power-on reset (POR) macrocell to ensure correct device initialization and operation of all macrocells in the

device. The purpose of the POR circuit is to have consistent behavior and predictable results when the VDD power is first ramping

to the device, and also while the VDD is falling during power-down. To accomplish this goal, the POR drives a defined sequence

of internal events that trigger changes to the states of different macrocells inside the device, and finally to the state of the I/O pins.

This application note is created to explain the whole process of POR operation and GreenPAK chip behavior during the time while

it is powering up and powering down.

15.1 General Operation

The SLG46110 is guaranteed to be powered down and nonoperational when the VDD voltage (voltage on PIN1) is less than 0.6V,

but not less than -0.6V. Another essential condition for the chip to be powered down is that no voltage higher (see Note 1) than

the VDD voltage is applied to any other PIN. For example, if VDD voltage is 0.3V, applying a voltage higher than 0.3V to any other

PIN is incorrect, and can lead to incorrect or unexpected device behavior.

Note 1. There is a 0.6V margin due to forward drop voltage of the ESD protection diodes.

To start the POR sequence in the SLG46110, the voltage applied on the VDD should be higher than the Power_ON threshold

(see Note 2). The full operational VDD range for the SLG46110 is 1.71V – 5.5V (1.8V ±5% - 5V±10%). This means that the VDD

voltage must ramp up to the operational voltage value, but the POR sequence will start earlier, as soon as the VDD voltage rises

to the Power_ON threshold. After the POR sequence has started, the SLG46110 will have a typical period of time to go through

all the steps in the sequence (noted in the datasheet for that device), and will be ready and completely operational after the POR

sequence is complete.

Note 2. The Power_ON threshold can vary by PVT, but typically it is 1.6V.

To power down the chip the VDD voltage should be lower than the operational and to guarantee that chip is powered down it

should be less than 0.6V.

All PINs are in high impedance state when the chip is powered down and while the POR sequence is taking place. The last step

in the POR sequence releases the I/O structures from the high impedance state, at which time the device is operational. The pin

configuration at this point in time is defined by the design programmed into the chip. Also as it was mentioned before the voltage

on PINs can’t be bigger than the VDD, this rule also applies to the case when the chip is powered on.

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