SLG46110V datasheet(24/82 Pages) DIALOG

24 / 82 page

000-0046110-106

Page 23 of 81

SLG46110

8.0 Connection Matrix

The Connection Matrix in the SLG46110 is used to create the internal routing for internal functions of the device once it is

programmed. The registers are programmed from the one-time NVM cell during Test Mode Operation. All of the connection point

for each logic cell within the SLG46110 has a specific digital bit code assigned to it that is either set to active “High” or inactive

“Low” based on the design that is created. Once the 512 register bits within the SLG46110 are programmed a fully custom circuit

will be created.

The Connection Matrix has 32 inputs and 44 outputs. Each of the 32 inputs to the Connection Matrix is hard-wired to a particular

source macrocell, including I/O pins, LUTs, analog comparators, other digital resources and VDD and VSS. The input to a digital

macrocell uses a 5-bit register to select one of these 32 input lines.

For a complete list of the SLG46110’s register table, see Section 16.0 Appendix A - SLG46110 Register Definition.

Figure 5. Connection Matrix

Figure 6. Connection Matrix Example

VSS

Pin 2 Digital In

Pin 3 Digital In

Pin 4 Digital In

Matrix Input Signal

Functions

PIN12 Digital In

VDD

Function

Registers

PIN12 Digital Output

Source

reg <219:215>

PIN3 Digital Output

Source

reg <4:0>

PIN4Digital Output

Source

reg <9:5>

PIN6 Digital Output

Source

reg <14:10>

Matrix Inputs

Matrix Outputs

Pin 2

Pin 3

Pin 10

Connection Matrix

LUT

Pin 3

Pin 2

LUT

Pin 10

Function

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