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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SLG46110V датащи(PDF) 11 Page - Dialog Semiconductor |
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SLG46110V датащи(HTML) 11 Page - Dialog Semiconductor |
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11 / 82 page  000-0046110-106 Page 10 of 81 SLG46110 5.5 IDD Estimator 5.6 Timing Estimator Table 1. Typical Current estimated for each macrocell. Symbol Parameter Note VDD = 1.8 V VDD = 3.3V VDD = 5.0V Unit I Current Chip Quiescent 0.5 0.8 1.0 A Vref 56.9 56.9 63.3 A Vref Buffer (each) 2.7 13.0 13.7 A OSC 25 kHz, predivide = 1 3.1 4.8 6.4 A OSC 25 kHz, predivide = 8 3.0 4.5 6.0 A OSC 2 MHz, predivide = 1 27.4 45.4 67.4 A OSC 2 MHz, predivide = 8 17.5 23.7 29.5 A 1st ACMP used (includes Vref) 60.6 62.0 68.4 A Each additional ACMP add 3.7 4.9 5.1 A Table 2. Typical Delay estimated for each macrocell. Symbol Parameter Note VDD = 1.8 V VDD = 3.3V VDD = 5.0V Unit rising falling rising falling rising falling tpd Delay Digital Input without Schmitt Trigger - Push Pull 35.3 34.4 14.5 14.3 10.3 10.5 ns tpd Delay Digital Input with Schmitt Trigger - Push Pull 34.8 32.9 14.2 13.8 10.0 10.1 ns tpd Delay Low Voltage Digital input - Push Pull 37.8 450.0 15.0 208.2 10.5 142.3 ns tpd Delay Digital Input without Schmitt Trigger -- NMOS — 73.5 — 26.0 — 16.3 ns tpd Delay Output enable from pin, OE Hi-Z to 1 44.6 — 17.9 — 12.4 — ns tpd Delay Output enable from pin, OE Hi-Z to 0 — 43.0 — 17.6 — 12.5 ns tpd Delay 2-bit LUT (Latch shared macrocell inputs) 29.6 24.8 11.5 10.1 8.2 6.9 ns tpd Delay Latch (2-bit LUT shared macrocell inputs) 29.2 31.5 11.8 12.5 8.4 8.4 ns tpd Delay 3-bit LUT (LATCH shared macrocell inputs) 33.0 27.4 12.8 11.1 9.1 7.5 ns tpd Delay Latch with nRST/nSET (3-bit LUT shared macrocell inputs) 29.9 32.4 12.1 13.0 8.7 8.7 ns tpd Delay 4-bit LUT (shared macrocell inputs) 29.2 27.2 11.2 10.8 8.0 7.3 ns tpd Delay 2-bit LUT 19.4 18.8 7.2 7.4 5.1 5.0 ns tpd Delay 3-bit LUT 22.3 22.7 8.3 8.9 6.0 5.9 ns tpd Delay CNT/DLY 38.4 36.0 15.2 15.1 10.8 10.4 ns tpd Delay CNT/DLY (shared macrocell inputs) 41.0 36.2 16.3 15.6 11.5 10.9 ns tpd Delay CNT3/DLY3 Rising Edge Detect (shared macrocell inputs) 39.7 — 15.7 — 11.1 — ns tpd Delay CNT3/DLY3 Falling Edge Detect (shared macrocell inputs) — 41.5 — 16.9 — 11.6 ns tpd Delay CNT3/DLY3 Both Edge Detect (shared macrocell inputs) 39.7 41.5 15.7 16.9 11.1 11.6 ns tpd Delay Filter 183.1 186.2 73.5 75.7 47.9 50.2 ns |
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