SLG46110V datasheet(70/82 Pages) DIALOG

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000-0046110-106

Page 69 of 81

SLG46110

Counter/Delay 1

reg <341:328>

reg <328> Counter/delay1 mode selection

0: Delay Mode

1: Counter Mode

reg <331:329> Counter/delay1 Clock Source select

(external clock is only for counter mode)

000: Internal OSC Clock

001: OSC/4

010: OSC/12

011: OSC/24

100: OSC/64

101: External Clock

110: External Clock

111: Counter0 Overflow

reg <339:332> Counter1 Control Data/Delay1 Time

Control

1-256: (delay time = (counter control data +2) /freq)

reg <341:340> Delay1 Mode Select or asynchronous

counter reset

00: Delay on both falling and rising edges(for delay

& counter reset)

01: Delay on falling edge only (for delay & counter

reset)

10: Delay on rising edge only (for delay & counter

reset)

11: No delay on either falling or rising edges / high

level reset for counter mode

Counter/Delay 3

reg <355:342>

reg <342> Counter/delay3 mode selection

0: Delay Mode

1: Counter Mode

reg <345:343> Counter/delay3 Clock Source select

(external clock is only for counter mode)

000: Internal OSC Clock

001: OSC/4

010: OSC/12

011: OSC/24

100: OSC/64

101: External Clock

110: External Clock

111: Counter2 Overflow

reg <353:346> Counter3 Control Data/Delay4 Time

Control

1-256: (delay time = (counter control data +2) /freq)

reg <355:354> Delay3 Mode Select

00: Delay on both falling and rising edges

01: Delay on falling edge only

10: Delay on rising edge only

11: No delay on either falling or rising edges

Address

Signal Function

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