SLG46110V datasheet(75/82 Pages) DIALOG

75 / 82 page

000-0046110-106

Page 74 of 81

SLG46110

PIN12

reg <431:425>

reg <427:425> PIN12 mode control

000: Digital Input without Schmitt trigger

001: Digital Input with Schmitt trigger

010: Low voltage digital input

011: Analog Input / Output

100: Push Pull

101: Open Drain NMOS

110: Open Drain PMOS

111: Analog Input / Output & Open drain

reg <429:428> PIN12 pull up/down resistor value selec-

tion

00: floating

01: 10K

10: 100K

11: 1M

reg <430> PIN12 pull up/down resistor select

0: pull down resistor enable

1: pull up resistor enable

reg <431> PIN12 driver strength selection

0: 1X

1: 2X

reg <432>

Pipe delay OUT1 polarity select bit

0: non-inverting

1: inverting

reg <440:433>

8-bit pattern id

reg <441>

filter0 output polarity select

0: non-inverting

1: inverting

reg <443:442>

Reserved

reg <444>

GPIO quick charge enable

0: Disable

1: Enable

reg <445>

Force bandgap on

0: Auto-mode

1: Enable

reg <446>

VREF1 Output Active Buffer Control

0: Disabled

1: Enabled

reg <449:447>

VREF1 Output Source Select

000: ACMP0 reference voltage

001: ACMP1 reference voltage

100: VDD/2

101: VDD/3

110: VDD/4

101: Reserved

110: Reserved

111: Reserved

reg <450>

NVM data read disable

0: Disable (read enable)

1: Enable (read disable)

reg <451>

NVM power down (or NVM data programming disable) 0: None (or programming enable)

1: Power Down (or programming disable)

reg <452>

Power Divider Power

0: Power down

1: Power On

reg <453>

POR Auto Power detect

0: Enable

1: Disable

reg <454>

Charge pump for analog macrocell enable (when VDD

<= 2.7 V turn on)

0: Disable (automatic on/off control)

1: Enable (always on)

reg <455>

VDD bypass enable

0: Regulator auto on

1: Regulator off (VDD bypass)"

reg <471:456>

Reserved

reg <479:472>

Reserved

Address

Signal Function

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