SLG46110V datasheet(69/82 Pages) DIALOG

69 / 82 page

000-0046110-106

Page 68 of 81

SLG46110

reg <303>

RC Oscillator frequency control

0: 25k

1: 2M

reg <305:304>

Osc clock pre-divider

00: div1

01: div2

10: div4

11: div8

reg <308:306>

Internal Oscillator frequency divider control 0 for Matrix

Input

000: OSC/1

001: OSC/2

010: OSC/3

011: OSC/4

100: OSC/8

101: OSC/12

110: OSC/24

111: OSC/64

reg <311:309>

Internal Oscillator frequency divider control 1 for Matrix

Input

000: OSC/1

001: OSC/2

010: OSC/3

011: OSC/4

100: OSC/8

101: OSC/12

110: OSC/24

111: OSC/64

reg <312>

External Clock Source Select

0: Internal Oscillator

1: External Clock from PIN12

reg <313>

Reserved

Counter/Delay 0

reg <327:314>

reg <314>Counter/delay0 mode selection

0: Delay Mode

1: Counter Mode

reg <317:315> Counter/delay0 Clock Source select

(external clock is only for counter mode)

000: Internal OSC Clock

001: OSC/4

010: OSC/12

011: OSC/24

100: OSC/64

101: External Clock

110: External Clock

111: Counter3 Overflow

reg <325:318> Counter0 Control Data/Delay0 Time

Control

1-256: (delay time = (counter control data +2) /freq)

reg <327:326> Delay0 Mode Select or asynchronous

counter reset

00: Delayon both falling and rising edges(for delay &

counter reset)

01: Delayon falling edge only (for delay & counter

reset)

10: Delayon rising edge only (for delay & counter

reset)

11: No delay on either falling or rising edges / high

level reset for counter mode

Address

Signal Function

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