SLG46110V datasheet(41/82 Pages) DIALOG

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000-0046110-106

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SLG46110

10.4.2 4-Bit LUT or 8-Bit Counter / Delay Macrocells Used as 8-Bit Counter / Delay Register Settings

10.5 Programmable Delay / Edge Detector

The SLG46110 has a programmable time delay logic cell available that can generate a delay that is selectable from one of four

timings (time1) configured in the GreenPAK Designer. The programmable time delay cell can generate one of four different delay

patterns, rising edge detection, falling edge detection, both edge detection and both edge delay. These four patterns can be further

modified with the addition of delayed edge detection, which adds an extra unit of delay as well as glitch rejection during the delay

period. See the timing diagrams below for further information.

Note

: The input signal must be longer than the delay, otherwise it will be filtered out.

Table 34. CNT/DLY2 Register Settings

Signal Function

Address

Counter/delay2

Mode Selection

reg <285>

0: Delay Mode

1: Counter Mode

Counter/delay2

Clock Source Select

reg <288:286>

000: Internal OSC Clock

001: OSC/4

010: OSC/12

011: OSC/24

100: OSC/64

101: External Clock

110: External Clock

111: Counter1 Overflow

Counter/delay2

Control Data

reg <296:289>

1 – 256 (delay time = (counter control data +2) /freq)

Delay2 Mode Select

or asynchronous

counter reset

reg <298:297>

00: Delay on both falling and rising edges(for delay & counter reset)

01: Delay on falling edge only (for delay & counter reset)

10: Delay on rising edge only (for delay & counter reset)

11: No delay on either falling or rising edges / high level reset for counter mode

LUT4_0 or Count-

er2 select

reg <301>

0: LUT4_0

1: Counter2

Figure 15. Programmable Delay

Programmable

Delay

OUT

reg <489:488>

From Connection

Matrix Output <37>

To Connection

Matrix Input <22>

reg <487:486>

Edge Mode Selection

Delay Value Selection

reg <485>

Deglitch Filter Out

reg <485>

Deglitch Filter In

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