CS4399 datasheet(37/111 Pages) CIRRUS

номер детали	CS4399

подробное описание детали	130-dB, 32-Bit High-Performance DAC

PDF	111 Pages

Scroll/Zoom	100%

производитель	CIRRUS [Cirrus Logic]

домашняя страница	http://www.cirrus.com

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37 / 111 page

DS1113F1

CS4399

4.8 Audio Serial Port (ASP)

The LRCK-high width (xSP_LCHI) controls the number of SCLK periods for which the LRCK signal is held high during

each frame. Like the LRCK period, the LRCK-high width is programmable in single SCLK periods, from a minimum of one

period to a maximum of the LRCK period minus one (and an absolute maximum of 768 SCLK periods). That is, LRCK-high

width must be less than the LRCK period.

Figure 4-19. xSP LRCK Period, High Width

As shown in Fig. 4-20, if Serial Port 50/50 Mode is enabled (xSP_5050 = 1), the LRCK high duration must be programmed

to the LRCK period divided by two (rounded down to the nearest integer when the LRCK period is odd). When the serial

port is in 50/50 Mode, setting the LRCK high duration to a value other than half of the period results in erroneous operation.

Figure 4-20. xSP_LRCK Period, High Width, 50/50 Mode

SCLK

LRCK

Falling

Edge

Rising

Edge

xSP_LCPR

xSP_LCHI

...

SCLK

LRCK

Falling

Edge

Rising

Edge

xSP_LCPR

xSP_LCHI

SCLK

LRCK

Falling

Edge

Rising

Edge

xSP_LCPR

xSP_LCHI

Even xSP _LCPR

Odd xSP _LCPR

xSP_LCPR count clock is absent

xSP_LCHI

...

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