CS4399 datasheet(18/111 Pages) CIRRUS

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DS1113F1

CS4399

3 Characteristics and Specifications

Table 3-14. Power Consumption

Test conditions (unless specified otherwise): Fig. 2-1 shows CS4399 connections; GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground;

performance data taken with VA = VCP = VD = VL = 1.8 V; VP = 3.6 V; TA = +25°C; ASP_SPRATE = 0001(44.1-kHz mode); MCLK_INT= 1

(22.5792 MHz); MCLK_SRC_SEL = 00; all other fields are set to defaults; no signal on any input; control port inactive; all serial ports are set to Slave or

Master Mode as indicated, input clock/data are held low unless active; test load is RL = 600  and CL = 1 nF for AOUTx; measured values include currents

consumed by the DAC and do not include current delivered to external loads unless specified otherwise (e.g., from AOUTx outputs); see Fig. 2-1.

Use Cases

Typical Current (µA)

Total

Power

(µW)

POUT

iVCP

iVA

iVD

iVL

iVP

1Off 1

1.Off configuration: Clock/data lines held low; RESET = LOW; VA = VD = VL = 0 V, VCP = 0 V, VP = 3.6 V.

—0

Standby 2

2.Standby configuration: Clock/data lines held low; RESET = HIGH; VA = VD = VL = 1.8 V, VCP = 1.8 V, VP = 3.6 V; HP_DETECT_CTRL = 11 (enabled);

HPDETECT_PLUG_INT_MASK=0 (unmasked); PDN_XTAL = 1, MCLK_SRC_SEL = 10 (RCO selected as MCLK source).

HPDETECT enabled

—

256

576

3 A Playback

External MCLK = 22.5792 MHz, I2S/DoP

Stereo AOUT

Quiescent 3

3.Quiescent configuration: data lines held low; RESET = HIGH; VA = 1.8 V, VD = VL = VCP = 1.8 V, VP = 3.6 V. Serial port, I2S/DoP Mode (ASP and

SDIN, ASP_M/Sb = 0); PDN_XTAL = 1.

4021

7302

1444

23167

Table 3-15. Serial-Port Interface Characteristics

Test conditions (unless specified otherwise): Fig. 2-1 shows CS4399 connections; GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground;

parameters can vary with VL; typical performance data taken with VL = VD = VA = VCP = 1.8 V, VP = 3.6 V; min/max performance data taken with VL =

1.8 V; VD = VA = VCP = 1.8 V, VP = 3.6 V; TA = +25°C; CL = 60 pF; Logic 0 = ground, Logic 1 = VL; output timings are measured at VOL and VOH thresholds

(see Table 3-8).

Parameters 1,2,3,4,5

1.MCLK in this table refers to the external clock supplied to the MCLK pin (MCLKEXT).

2.Output clock frequencies follow the master clock (MCLKEXT) frequency proportionally. Any deviation of the clock source from the nominal supported

rates are directly imparted to the output clock rate by the same factor (e.g., +100-ppm offset in the frequency of MCLKEXT becomes a +100-ppm

offset in LRCK/FSYNC and SCLK).

3.I2S interface timing

Symbol

Minimum

Typical

Maximum

Units

FSYNC frame rate

(See

Section 4.8.5)

kHz

FSYNC high period 6

tHI:FSYNC

1/fSCLK

—

(n–1)/fSCLK

Master

Mode

FSYNC duty cycle

xSP_5050 = 1

—

FSYNC delay time after SCLK launching edge 7

tD:CLK–FSYNC

——20

SCLK frequency

fSCLK

——

fMCLK_INT

MHz

SCLK high period 8

tHI:SCLK

1/(2•fSCLK) –

1/fMCLK_INT

—1/(2•fSCLK) +

1/fMCLK_INT

SDIN setup time before SCLK latching edge 7

tSU:SDI

—

SDIN hold time after SCLK latching edge 7

tH:SDI

5—

—

Slave

Mode

FSYNC setup time before SCLK latching edge 7

tSU:FSYNC

—

FSYNC hold time after SCLK latching edge 7

tH:FSYNC

5—

—

SCLK frequency

fSCLK

——

24.58

MHz

SCLK high period

tHI:SCLK

—

SCLK low period

tLO:SCLK

—

SDIN setup time before SCLK latching edge 9

tSU:SDI

—

SDIN hold time after SCLK latching edge 7

tH:SDI

5—

—

SCLK

(CPOL = 1)

SDIN

tSU:SDI

tH:SDI

LRCK/FSYNC

tD:CLK–FSYNC

1/Fs

...

fSCLK = N · Fs

tSU:FSYNC

tH:FSYNC

tLO:SCLK

tHI:SCLK

SCLK

(CPOL = 0)

...

1/fSCLK

...

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