CS4399 datasheet(31/111 Pages) CIRRUS

31 / 111 page

DS1113F1

CS4399

4.6 Clock Output and Fractional-N PLL

Further restrictions are listed in Table 4-3.

Figure 4-13. MCLK Source Switching

A source to MCLK_INT, either the XTAL (or external MCLK), the PLL, or the RCO, must be provided as long as the

CS4399 is operating; otherwise, the CS4399 enters a nonresponsive state, and I2C SDA signal can be held low. The only

way to recover from this nonresponsive state is either through a reset or a POR event. Switching MCLK sources during

DAC operation causes audible artifacts, but does not put the device in an unrecoverable state. In an MCLK

source-switching event, the intended clock source must be present and ready before switching occurs.

After POR or reset event, RCO is selected as default source of MCLK_INT.

4.5.1.1 Internal RC Oscillator

As described in Section 4.5.1, the CS4399 includes an internal RC oscillator that can be used as a clock source for

peripheral circuit such as control port or charge pump.

4.6 Clock Output and Fractional-N PLL

The CS4399 clock output can be used as a master clock for other data-conversion or signal-processing components,

which requires synchronous timing to the CS4399.

Table 4-3. MCLK Source Restrictions

Internal

MCLK

Source

MCLK_SRC_SEL MCLK_INT

Restrictions

Direct MCLK

or XTAL

• Nominal MCLK_INT frequency = 24.576 MHz

• All specified CLKOUT frequencies (generated by PLL or XTAL) are supported

• CLKOUT outputs (/2, /3, /4, /8 divide) optionally

• Nominal MCLK_INT frequency = 22.5792 MHz

• All specified CLKOUT frequencies (generated by PLL or XTAL) are supported

• CLKOUT outputs (/2, /3, /4, /8 divide) optionally

PLL

• Nominal MCLK_INT frequency = 24.576 MHz

• PDN_PLL = 0 and PLL properly configured to generate 24.576 MHz given reference input

frequency on XTI/MCLK pin

• Only MCLK_INT on CLKOUT is supported on CLKOUT pin

• CLKOUT outputs (/2, /3, /4, /8 divide) optionally

• Nominal MCLK_INT frequency = 22.5792MHz

• PDN_PLL = 0 and PLL properly configured to generate 22.5792 MHz given reference input

frequency on XTI/MCLK pin

• Only MCLK_INT on CLKOUT is supported on CLKOUT pin

• CLKOUT outputs (/2, /3, /4, /8 divide) optionally

Internal

PLL

XTI/MCLK

Internal MCLK

CLKOUT

CLKOUT_SEL p. 77

PDN_PLL p. 75

CLKOUT_DIV p. 77

MCLK_INT p. 73

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