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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS4399 датащи(PDF) 82 Page - Cirrus Logic |
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CS4399 датащи(HTML) 82 Page - Cirrus Logic |
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82 / 111 page  82 DS1113F1 CS4399 7.3 ASP and XSP Registers 2XSP_SCPOL_ IN XSP SCLK input polarity (pad to logic). 0Normal 1 (Default) Inverted 1 XSP_LCPOL_ OUT XSP LRCK output drive polarity. 0 (Default) Normal 1Inverted 0 XSP_LCPOL_ IN XSP LRCK input polarity (pad to logic). 0 (Default) Normal 1Inverted 7.3.21 XSP Frame Configuration Address 0x40029 R/W 76543210 — XSP_STP XSP_5050 XSP_FSD Default 00001010 Bits Name Description 7:5 — Reserved 4 XSP_STP XSP start phase. Controls which LRCK/FSYNC phase starts a frame. 0 (Default) The frame begins when LRCK/FSYNC transitions from high to low 1 The frame begins when LRCK/FSYNC transitions from low to high 3 XSP_5050 XSP LRCK fixed 50/50 duty cycle. 0 Programmable duty cycle per XSP_LCHI and XSP_LCPR 1 (Default) Fixed 50% duty cycle 2:0 XSP_FSD XSP frame start delay (units of XSP_SCLK periods). 000 0 delay 001 0.5 delay 010 (Default) 1.0 delay ... 101 2.5 delay 110–111 Reserved 7.3.22 ASP Channel 1 and 2 Location Address 0x50000, 0x50001 R/W 76543210 ASP_RX_CH1 ASP_RX_CH2 Default 00000000 Bits Name Description 7:0 ASP_RX_CHn ASP Rx channel n location. Sets the location in ASP_SCLK periods of the ASP Rx channel n from the start of the TDM frame. 0x00 Start on SCLK 0 ... 0xFF Start on SCLK 255 Defaults are 0x00. 7.3.23 ASP Channel 1 Size and Enable Address 0x5000A R/W 76543210 — ASP_RX_CH1_ AP ASP_RX_CH1_ EN ASP_RX_CH1_RES Default 00000110 7.3.24 ASP Channel 2 Size and Enable Address 0x5000B R/W 76543210 — ASP_RX_CH2_ AP ASP_RX_CH2_ EN ASP_RX_CH2_RES Default 00001110 Bits Name Description 7:4 — Reserved Bits Name Description |
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