CS4399 datasheet(36/111 Pages) CIRRUS

36 / 111 page

DS1113F1

CS4399

4.8 Audio Serial Port (ASP)

Fig. 4-17 and Fig. 4-18 show the serial port clocking architecture.

Figure 4-17. xSP SCLK and MCLK Architecture

As shown in Fig. 4-17, the master-mode SCLK output for each serial port is derived from the internal MCLK. The SCLK

output can be configured to various frequencies to accommodate many sample rates, sample sizes, and channel counts.

The SCLK is output of a fractional divide from the internal MCLK input, where N is the numerator and M is the denominator.

Note: Depending on the chosen fractional divide configuration, the SCLK duty cycle can vary by one MCLK period.

Input and output SCLK polarity controls (xSP_SCPOL_IN and xSP_SCPOL_OUT) are also available. As shown in

Fig. 4-17, if Master Mode is used, both polarity controls affect the SCLK used by the serial port module. For example, both

polarity controls must be set to invert (xSP_SCPOL_IN = xSP_SCPOL_OUT = 1) to invert the SCLK output and output

data on the falling edge. In typical use cases, the values of xSP_SCPOL_IN equals xSP_SCPOL_OUT in each serial port.

See Fig. 4-20 for example waveforms showing the various settings of the SCLK polarity controls.

Likewise, input and output LRCK polarity controls (xSP_LCPOL_IN and xSP_LCPOL_OUT) are available. In Master

Mode, both LRCK polarity controls affect the LRCK used by the serial-port module as shown in Fig. 4-18. In typical-use

cases, the value of xSP_LCPOL_IN equals xSP_LCPOL_OUT in each serial port.

Figure 4-18. xSP LRCK Architecture

As shown in Fig. 4-19, xSP_LCPR determines the LRCK/FSYNC period, in units of SCLK periods. The LRCK period

effectively sets the length of the frame and the number of SCLK periods per Fs. Frame length may be programmed in

single SCLK period multiples from a minimum of 16 SCLK:Fs up to 1536 SCLK:Fs.

Internal MCLK

N[13:0]

M[13:0]

SCLK

To LRCK

SCLK to

Serial Port

ASP_SCPOL_IN p. 79/

XSP_SCPOL_IN p. 82

ASP_M/SB p. 79/

XSP_M/SB p. 81

ASP_SCPOL_OUT p. 79/

XSP_SCPOL_OUT p. 81

ASP_M_LSB p. 78/XSP_M_LSB p. 80

ASP_M_MSB p. 78/XSP_M_MSB p. 80

ASP_N_LSB p. 77/XSP_N_LSB p. 80

ASP_N_MSB p. 78/XSP_N_MSB p. 80

LRCK to

Serial Port

ASP_LRCK/FSYNC

PER

OUT

LR GEN

From SCLK

x_M/S = 1 (master) &

PDN_x = 0 (enabled )

5050

DELAY

ASP_5050 p. 79/XSP_5050 p. 82

ASP_FSD p. 80/XSP_FSD p. 82

ASP_LCPOL_IN p. 79/

XSP_LCPOL_IN p. 82

ASP_M/SB p. 79/

XSP_M/SB p. 81

ASP_LCPOL_OUT p. 79/

XSP_LCPOL_OUT p. 82

ASP_LCHI_LSB p. 78/XSP_LCHI_LSB p. 81

ASP_LCHI_MSB p. 78/XSP_LCHI_MSB p. 81

ASP_LCPR_LSB p. 79/XSP_LCPR_LSB p. 81

ASP_LCPR_MSB p. 79/XSP_LCPR_MSB p. 81

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