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CS4399 датащи(PDF) 30 Page - Cirrus Logic

номер детали CS4399
подробное описание детали  130-dB, 32-Bit High-Performance DAC
PDF  111 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS4399 датащи(HTML) 30 Page - Cirrus Logic

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DS1113F1
CS4399
4.5 Clocking Architecture
When the MCLK is supplied to the device through the XTI/MCLK pin, it must comply with the phase-noise mask shown in
Fig. 4-11. Its frequency must be one of the nominal MCLK_INT frequencies (22.5792 or 24.576 MHz), and its duty cycle
must be between 45% to 55%.
Figure 4-11. MCLK Phase Noise Mask Without PLL
When the PLL reference clock is supplied to the device through the XTI/MCLK pin, it must comply with the phase-noise
mask shown in Fig. 4-12.
Figure 4-12. MCLK Phase Noise Mask With PLL



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