CS4399 datasheet(46/111 Pages) CIRRUS

46 / 111 page

DS1113F1

CS4399

4.12 Control Port Operation

The control-port uses the I2C interface, with the chip acting as a slave device. The I2C control port can operate in the

following modes:

• Standard Mode (SM), with a bit rate of up to 100 kbit/s

• Fast Mode (FM), with a bit rate of up to 400 kbit/s

• Fast Mode Plus (FM+), with a bit rate of up to 1 Mbit/s

SDA is a bidirectional data line. Data is clocked into and out of the CS4399 by the SCL clock. Fig. 4-29, Fig. 4-30, and

Fig. 4-31 show signal timings for read and write cycles. A Start condition is defined as a falling transition of SDA while SCL

is high. A stop condition is defined as a rising transition of SDA while SCL is high. All other transitions of SDA must occur

while SCL is low.

To configure the last two bits of I2C address, CS4399 detects the ADR resistor connection type and measures the

resistance upon a device power up (POR event) or after a hardware reset event (RESET deasserted). Based on the

detected resistance, the I2C address is latched and cannot be changed until the next hardware reset event. The I2C

address configuration is not ready until tPUD after the hardware reset event. During this period, the CS4399 does not

respond to any user-issued I2C command. After configuration, the IC tristates the ADR pin and becomes high impedance

internally to avoid a constant bias current.

When the ADR pin is directly connected to ground, the last two bits of the I2C address are configured as 00 (default). For

the other options, use a resistor (with 5% accuracy) as suggested in the Table 4-12.

If the operation is a write, the 3 bytes after the chip address are the memory address pointer (MAP) that select the address

of the register to be read or written to next. The byte following the MAP is the control byte. Bit[0] of the control byte, INCR,

selects whether autoincrementing is to be used (INCR = 1), allowing successive reads or writes of consecutive registers.

Bits[2:1] of the control byte indicate the size of the data for the autoincrement to be acted on. Table 4-13 explains the

format for the I2C control byte.

Each byte transferred on the I2C bus is separated by an acknowledge (ACK) bit. The CS4399 acknowledges each input

byte read from the host, and the host must acknowledge each byte transmitted from the CS4399.

Table 4-12. I2C Address Configurations

Connection Type

Resistor Value (

)

Last Two Bits of I2C Address

Pull-up to VL

4990

Pull-down to GND

4990

Pull-down to GND

00 (Default)

Table 4-13. I2C Control-Byte Format

Bit

Name

Description

7:3

—

Reserved

Default: 0

2:1

SIZE

00 8-bit (1 byte)

01–11 Reserved

INCR

Setting this bit allows the MAP address to autoincrement. The MAP address automatically increments every SIZE + 1 bytes

accessed consecutively.

0 Disabled

1 Enabled

CS4399 датащи(PDF) 46 Page - Cirrus Logic

CS4399 датащи(HTML) 46 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL