CS4399 datasheet(32/111 Pages) CIRRUS

32 / 111 page

DS1113F1

CS4399

4.6 Clock Output and Fractional-N PLL

The CLKOUT output is enabled by clearing PDN_CLKOUT.

Figure 4-14. CLKOUT Source Selection

Once enabled, CLKOUT is generated either from the internal crystal oscillator output (when used) or from the integrated

fractional-N PLL; it can be selected by CLKOUT_SEL. CLKOUT_DIV can be used to set /2, /3, /4, or /8 to divide the

selected clock source to targeted frequency.

4.6.1

Fractional-N PLL

The CS4399 has an integrated fractional-N PLL to support the clocking requirements of various applications. This PLL can

be enabled or disabled by clearing or setting PDN_PLL bit. The input reference clock for the PLL is signal on XTI/MCLK

pin (crystal-generated or external-feed).

4.6.2

Fractional-N PLL Internal Interface

Fig. 4-15 shows how PLL operation can be configured.

Figure 4-15. Fractional-N PLL

Use Eq. 4-1 to calculate the PLL output frequency.

Equation 4-1. PLL Output Frequency Equation

PLL_REF source must be in range below:

PLL_REF Source

PLL_REF_PREDIV Input

Minimum

Maximum

MCLK/XIN pin

9.6 MHz

26 MHz

XTI/MCLK

PLL_OUT

CLKOUT

CLKOUT_DIV

CLKOUT_SEL p. 77

PLL

XTI/MCLK

PLL_OUT

PLL_DIV_INT p. 76

PLL_DIV_FRAC_0 p. 76

PLL_DIV_FRAC_1 p. 76

PLL_DIV_FRAC_2 p. 76

PLL_MODE p. 77

PLL_REF_

PREDIV

p. 77

PDN_PLL p. 75

PLL_START p. 75

PLL_OUT_

DIV p. 76

PLL_OUT =

PLL_REF

PLL_REF_PREDIV

PLL_OUT_DIV

PLL_DIV_INT + PLL_DIV_FRAC

or 1, selected by PLL_Mode

500

512

CS4399 датащи(PDF) 32 Page - Cirrus Logic

CS4399 датащи(HTML) 32 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL