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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS4399 датащи(PDF) 20 Page - Cirrus Logic |
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CS4399 датащи(HTML) 20 Page - Cirrus Logic |
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20 / 111 page  20 DS1113F1 CS4399 3 Characteristics and Specifications Rise time of SCL and SDA Standard Mode Fast Mode Fast Mode Plus tRC — — — 1000 300 120 ns ns ns Fall time of SCL and SDA Standard Mode Fast Mode Fast Mode Plus tFC — — — 300 300 120 ns ns ns Setup time for stop condition tSUSP 260 — ns SDA setup time to SCL rising tSUD 50 — ns SDA input hold time from SCL falling 4 tHDDI 0— ns Output data valid (Data/Ack) 5 Standard Mode Fast Mode Fast Mode Plus tVDDO — — — 3450 900 450 ns ns ns Bus free time between transmissions tBUF 500 — ns SDA bus capacitance SCL frequency = 1 MHz, VL = 1.8 V SCL frequency ≤ 400 kHz CB — — 400 400 pF pF SCL/SDA pull-up resistance 1 VL = 1.8 V RP 350 — Ω Pulse width of spikes to be suppressed tPS —50 ns Switching time between RCO and MCLK_INT 6 — 150 — µs Power-up delay (delay before I2C can communicate after RESET released) tPUD 1500 — µs 1.The minimum RP value (resistor shown in Fig. 2-1) is determined by using the maximum level of VL, the minimum sink current strength of its respective output, and the maximum low-level output voltage VOL. The maximum RP value may be determined by how fast its associated signal must transition (e.g., the lower the value of RP, the faster the I2C bus is able to operate for a given bus load capacitance). See I²C bus specification referenced in Section 13. 2.All timing is relative to thresholds specified in Table 3-8, VIL and VIH for input signals, and VOL and VOH for output signals. 3.I²C control-port timing 4.Data must be held long enough to bridge the transition time, tF, of SCL. 5.Time from falling edge of SCL until data output is valid. 6.Upon setting MCLK_SRC_SEL and sending the I2C stop condition, the switching of RCO and other MCLK_INT sources occurs. A least wait time as specified is required after changing MCLK_SRC_SEL and sending the I2C stop condition before the next I2C transaction is initiated. Table 3-17. I2C Slave Port Characteristics (Cont.) Test conditions (unless specified otherwise): Fig. 2-1 shows typical connections; Inputs: GNDA = GNDL = GNDCP = 0 V; all voltages with respect to ground; VL = 1.8 V; inputs: Logic 0 = GNDA = 0 V, Logic 1 = VL; TA = +25°C; SDA load capacitance equal to maximum value of CB = 400 pF; minimum SDA pull-up resistance, RP(min).1 Table 3-1 describes some parameters in detail. All specifications are valid for the signals at the pins of the CS4399 with the specified load capacitance. Parameter 2 Symbol 3 Minimum Maximum Units tBUF tLOW Stop tHDDI tSUD tSUST tRC tHDST tHIGH tHDST tFC tSUSP Start Repeated Start Stop SDA SCL tVDDO |
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