CS4399 datasheet(19/111 Pages) CIRRUS

19 / 111 page

DS1113F1

CS4399

3 Characteristics and Specifications

4.TDM interface timing

(shown with xSP_FSD = 010, xSP_LCHI = 1)

5.Applies to Master and Slave Modes, unless specified otherwise.

6.Maximum LRCK duty cycle is equal to frame length, in SCLK periods, minus 1. Maximum duty cycle occurs when LRCK high (xSP_LCHI) is set to

768 SCLK periods and LRCK period (xSP_LCPR) is set to 769 SCLK periods.

7.Data may be latched/launched on either the rising or falling edge of SCLK.

8.SCLK duty cycle in Master Mode depends on Master Mode clock configuration, and can vary by up to 1 MCLKEXT period.

9.Data is latched/launched on the rising or falling edge of SCLK as determined by xSP_SCPOL_OUT, xSP_SCPOL_IN, and xSP_FSD bits. See the

SCLK launching specs in Table 3-15.

Table 3-16. DSD Switching Characteristic

Test conditions (unless specified otherwise): Fig. 2-1 shows CS4399 connections; GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground;

parameters can vary with VL; typical performance data taken with VL = VD = VA = VCP = 1.8 V, VP = 3.6 V; min/max performance data taken with VL =

1.8 V; VD = VA = VCP = 1.8 V, VP = 3.6 V; TA = +25°C; CL = 60 pF; Logic 0 = ground, Logic 1 = VL; output timings are measured at VOL and VOH

thresholds (see Table 3-8).

Parameter 1,2

1.Serial audio input interface timing

2.Phase modulation mode serial audio input interface timing

Symbol

Minimum

Typical

Maximum

Units

DSDCLK duty cycle

—

DSDCLK pulse width low

tSCLKL

—

DSDCLK pulse width high

tSCLKH

—

DSDCLK frequency

(64× oversampled)

(128× oversampled)

—

1.024

2.048

2.8224

5.6448

fMCLK_INT/8

fMCLK_INT/4

MHz

DSDA/DSDB valid to DSDCLK rising setup time

tSDLRS

—

DSDCLK rising to DSDA or DSDB hold time

tSDH

—

DSD clock to data transition (Phase Modulation Mode)

tDPM

–20

—

Table 3-17. I2C Slave Port Characteristics

Test conditions (unless specified otherwise): Fig. 2-1 shows typical connections; Inputs: GNDA = GNDL = GNDCP = 0 V; all voltages with respect to

ground; VL = 1.8 V; inputs: Logic 0 = GNDA = 0 V, Logic 1 = VL; TA = +25°C; SDA load capacitance equal to maximum value of CB = 400 pF; minimum

SDA pull-up resistance, RP(min).1 Table 3-1 describes some parameters in detail. All specifications are valid for the signals at the pins of the CS4399 with

the specified load capacitance.

Parameter 2

Symbol 3

Minimum

Maximum

Units

SCL clock frequency

fSCL

—1000

kHz

Clock low time

tLOW

500

—

Clock high time

tHIGH

260

—

Start condition hold time (before first clock pulse)

tHDST

260

—

Setup time for repeated start

tSUST

260

—

SCLK

SDIN

tSU:SDI

tH:SDI

LRCK/FSYNC

tD:CLK-FSYNC

1/fSCLK

Don’t Care

Frame location 0

Frame location N -1

1/Fs

...

fSCLK = N · Fs

tSU :FSYNC

tH:FSYNC

tHI:FSYNC

tLO:SCLK

tHI:SCLK

DSDCLK

DSDA,

DSDB

tSDLRS

tSDH

tSCLKL

tSCLKH

DSDCLK

(128

•Fs)

DSDCLK

(64

•Fs)

DSDA,

DSDB

tDPM

CS4399 датащи(PDF) 19 Page - Cirrus Logic

CS4399 датащи(HTML) 19 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL