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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SPC56EL70L3 датащи(PDF) 115 Page - STMicroelectronics |
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SPC56EL70L3 датащи(HTML) 115 Page - STMicroelectronics |
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115 / 128 page  DocID023953 Rev 5 115/128 SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5 Electrical characteristics 127 Figure 29. External interrupt timing 3.20.6 DSPI timing Table 39. DSPI timing No. Symbol Parameter Conditions Min Max Unit 1tSCK D DSPI cycle time Master (MTFE = 0) 62 — ns DSlave (MTFE = 0) 62 — D Slave Receive Only Mode(1) 16 — 2tCSC D PCS to SCK delay — 16 — ns 3tASC D After SCK delay — 16 — ns 4tSDC D SCK duty cycle — tSCK/2 - 10 tSCK/2 + 10 ns 5tA D Slave access time SS active to SOUT valid — 40 ns 6tDIS D Slave SOUT disable time SS inactive to SOUT High-Z or invalid — 10 ns 7tPCSC D PCSx to PCSS time — 13 — ns 8tPASC DPCSS to PCSx time — 13 — ns 9tSUI D Data setup time for inputs Master (MTFE = 0) 20 — ns Slave 2— Master (MTFE = 1, CPHA = 0) 5— Master (MTFE = 1, CPHA = 1) 20 — 10 tHI D Data hold time for inputs Master (MTFE = 0) –5 — ns Slave 4 — Master (MTFE = 1, CPHA = 0) 11 — Master (MTFE = 1, CPHA = 1) –5 — 11 tSUO D Data valid (after SCK edge) Master (MTFE = 0) — 4 ns Slave — 23 Master (MTFE = 1, CPHA = 0) — 12 Master (MTFE = 1, CPHA = 1) — 4 IRQ 1 2 3 |
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