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SPC56EL70L3 датащи(PDF) 112 Page - STMicroelectronics |
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SPC56EL70L3 датащи(HTML) 112 Page - STMicroelectronics |
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112 / 128 page ![]() Electrical characteristics SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5 112/128 DocID023953 Rev 5 Figure 25. JTAG boundary scan timing 3.20.4 Nexus timing TCK Output Signals Input Signals Output Signals 11 12 13 14 15 Table 37. Nexus debug port timing(1) No. Symbol Parameter Conditions Min Max Unit 1tMCYC D MCKO Cycle Time — 15.6 — ns 2tMDC D MCKO Duty Cycle — 40 60 % 3tMDOV D MCKO Low to MDO, MSEO, EVTO Data Valid(2) —–0.1 0.25 tMCYC 4tEVTIPW D EVTI Pulse Width — 4.0 — tTCYC 5tEVTOPW D EVTO Pulse Width — 1 tMCYC 6tTCYC D TCK Cycle Time(3) — 62.5 — ns 7tTDC D TCK Duty Cycle — 40 60 % 8tNTDIS, tNTMSS D TDI, TMS Data Setup Time — 8 — ns 9tNTDIH, tNTMSH D TDI, TMS Data Hold Time — 5 — ns 10 tJOV D TCK Low to TDO Data Valid — 0 25 ns 1. JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. 2. For all Nexus modes except DDR mode, MDO, MSEO, and EVTO data is held valid until next MCKO low cycle. |
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