SPC56EL70L3 datasheet(19/128 Pages) STMICROELECTRONICS

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DocID023953 Rev 5

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SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5

Introduction

127

–

Option to enable/disable modulation to avoid protocol violation on jitter and/or

potential unadjusted error in electric motor control loop

–

Allows to run motor control periphery at different (precisely lower, equal or higher

as required) frequency than the system to ensure higher resolution

1.5.15

Main oscillator

The main oscillator provides these features:



Input frequency range 4–40 MHz



Crystal input mode



External reference clock (3.3 V) input mode



FMPLL reference

1.5.16

Internal reference clock (RC) oscillator

The architecture uses constant current charging of a capacitor. The voltage at the capacitor

is compared to the stable bandgap reference voltage. The RC oscillator is the device safe

clock.

The RC oscillator provides these features:



Nominal frequency 16 MHz



±5% variation over voltage and temperature after process trim



Clock output of the RC oscillator serves as system clock source in case loss of lock or

loss of clock is detected by the FMPLL



RC oscillator is used as the default system clock during startup and can be used as

back-up input source of FMPLL(s) in case XOSC fails

1.5.17

Clock, reset, power, mode and test control modules (MC_CGM,

MC_RGM, MC_PCU, and MC_ME)

These modules provide the following:



Clock gating and clock distribution control



Halt, stop mode control



Flexible configurable system and auxiliary clock dividers



Various execution modes

–

HALT and STOP mode as reduced activity low power mode

–

Reset, Idle, Test, Safe

–

Various RUN modes with software selectable powered modules

–

No stand-by mode implemented (no internal switchable power domains)

1.5.18

Periodic interrupt timer module (PIT)

The PIT module implements the following features:



4 general purpose interrupt timers



32-bit counter resolution



Can be used for software tick or DMA trigger operation

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