SPC56EL70L3 datasheet(31/128 Pages) STMICROELECTRONICS

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SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5

Introduction

127

–

Watchpoint trigger enable of program and/or data trace messaging

–

Data tracing of instruction fetches via private opcodes

1.5.39

IEEE 1149.1 JTAG controller (JTAGC)

The JTAGC block provides the means to test chip functionality and connectivity while

remaining transparent to system logic when not in test mode. All data input to and output

from the JTAGC block is communicated in serial format. The JTAGC block is compliant with

the IEEE standard.

The JTAG controller provides the following features:



IEEE Test Access Port (TAP) interface with 5 pins:

–TDI

–TMS

–TCK

–TDO

–JCOMP



Selectable modes of operation include JTAGC/debug or normal system operation



5-bit instruction register that supports the following IEEE 1149.1-2001 defined

instructions:

–BYPASS

–

IDCODE

–EXTEST

–SAMPLE

–

SAMPLE/PRELOAD



3 test data registers: a bypass register, a boundary scan register, and a device

identification register. The size of the boundary scan register is parameterized to

support a variety of boundary scan chain lengths.



TAP controller state machine that controls the operation of the data registers,

instruction register and associated circuitry

1.5.40

Voltage regulator / power management unit (PMU)

The on-chip voltage regulator module provides the following features:



Single external rail required



Single high supply required: nominal 3.3 V both for packaged and Known Good Die

option

–

Packaged option requires external ballast transistor due to reduced dissipation

capacity at high temperature but can use embedded transistor if power dissipation

is maintained within package dissipation capacity (lower frequency of operation)

–

Known Good Die option uses embedded ballast transistor as dissipation capacity

is increased to reduce system cost



All I/Os are at same voltage as external supply (3.3 V nominal)



Duplicated Low-Voltage Detectors (LVD) to guarantee proper operation at all stages

(reset, configuration, normal operation) and, to maximize safety coverage, one LVD

can be tested while the other operates (on-line self-testing feature)

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