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SPC56EL70L3 датащи(PDF) 28 Page - STMicroelectronics |
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SPC56EL70L3 датащи(HTML) 28 Page - STMicroelectronics |
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28 / 128 page ![]() Introduction SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5 28/128 DocID023953 Rev 5 1.5.33 Analog-to-Digital converter module (ADC) The ADC module features include: Analog part: 2 on-chip ADCs – 12-bit resolution SAR architecture – Same digital interface as in the SPC560P family – A/D Channels: 9 external, 3 internal and 4 shared with other A/D (total 16 channels) – One channel dedicated to each T-sensor to enable temperature reading during application – Separated reference for each ADC – Shared analog supply voltage for both ADCs – One sample and hold unit per ADC – Adjustable sampling and conversion time Digital part: 4 analog watchdogs comparing ADC results against predefined levels (low, high, range) before results are stored in the appropriate ADC result location 2 modes of operation: CPU Mode or CTU Mode CPU mode features – Register based interface with the CPU: one result register per channel – ADC state machine managing three request flows: regular command, hardware injected command, software injected command – Selectable priority between software and hardware injected commands – 4 analog watchdogs comparing ADC results against predefined levels (low, high, range) –DMA compatible interface CTU mode features – Triggered mode only – 4 independent result queues (1 16 entries, 28 entries, 14 entries) – Result alignment circuitry (left justified; right justified) – 32-bit read mode allows to have channel ID on one of the 16-bit parts –DMA compatible interfaces Built-in self-test features triggered by software 1.5.34 Cross triggering unit (CTU) The ADC cross triggering unit allows automatic generation of ADC conversion requests on user selected conditions without CPU load during the PWM period and with minimized CPU load for dynamic configuration. |
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