SPC56EL70L3 datasheet(99/128 Pages) STMICROELECTRONICS

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SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5

Electrical characteristics

127

3.16

Flash memory electrical characteristics

4. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal

resistance of the analog source must allow the capacitance to reach its final voltage level within tsample. After the end of the

sample time tsample, changes of the analog input voltage have no effect on the conversion result. Values for the sample

clock tsample depend on programming.

5. This parameter does not include the sample time tsample, but only the time for determining the digital result.

6. See Figure 9.

7. For the 144-pin package.

8. No missing codes.

Table 26. Flash memory program and erase electrical specifications

No.

Symbol

Parameter

Typ

(1)

Initial

Max(2)

Lifetime

Max(3)

Unit

1tDWPROGRAM

*(4)

Double word (64 bits) program time(4)

—

500

µs

2tPPROGRAM

*(4)

Page(128 bits) program time(4)

160

500

µs

3t16KPPERASE

*(4)

16 KB block pre-program and erase time

270

1000

5000

4t48KPPERASE

*(4)

48 KB block pre-program and erase time

625

1500

5000

5t64KPPERASE

*(4)

64 KB block pre-program and erase time

800

1800

5000

6t128KPPERASE

*(4)

128 KB block pre-program and erase time

1500 2600

7500

7t256KPPERASE

*(4)

256 KB block pre-program and erase time

3000 5200

15000

1. Typical program and erase times represent the median performance and assume nominal supply values and operation at

25 °C. These values are characterized, but not tested.I

2. Initial Max program and erase times provide guidance for time-out limits used in the factory and apply for < 100

program/erase cycles, nominal supply values and operation at 25°C. These values are verified at production test.

3. Lifetime Max program and erase times apply across the voltage, temperature, and cycling range of product life. These

values are characterized, but not tested.

4. Program times are actual hardware programming times and do not include software overhead.

Table 27. Flash memory timing

Symbol

Parameter

Value

Unit

Min

Typ

Max

tRES

Time from clearing the MCR-ESUS or PSUS bit with EHV = 1

until DONE goes low

——

100

tDONE

Time from 0 to 1 transition on the MCR-EHV bit initiating a

program/erase until the MCR-DONE bit is cleared

——

tPSRT

Time between program suspend resume and the next program

suspend request(1)

100

—

µs

tESRT

Time between erase suspend resume and the next erase

suspend request(2)

—

1. Repeated suspends at a high frequency may result in the operation timing out, and the flash module will respond by

completing the operation with a fail code (MCR[PEG] = 0), or the operation not able to finish (MCR[DONE] = 1 during

Program operation). The minimum time between suspends to ensure this does not occur is TPSRT.

2. If Erase suspend rate is less than TESRT, an increase of slope voltage ramp occurs during erase pulse. This improves erase

time but reduces cycling figure due to overstress.

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