SPC56EL70L3 datasheet(17/128 Pages) STMICROELECTRONICS

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SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5

Introduction

127

1.5.11

Peripheral bridge (PBRIDGE)

The PBRIDGE implements the following features:



Duplicated periphery



Master access right per peripheral (per master: read access enable; write access

enable)



Checker applied on PBRIDGE output toward periphery



Byte endianess swap capability

1.5.12

Interrupt controller (INTC)

The INTC provides priority-based preemptive scheduling of interrupt requests, suitable for

statically scheduled hard real-time systems.

For high-priority interrupt requests, the time from the assertion of the interrupt request from

the peripheral to when the processor is executing the interrupt service routine (ISR) has

been minimized. The INTC provides a unique vector for each interrupt request source for

quick determination of which ISR needs to be executed. It also provides an ample number

of priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To

allow the appropriate priorities for each source of interrupt request, the priority of each

interrupt request is software configurable.

The INTC supports the priority ceiling protocol for coherent accesses. By providing a

modifiable priority mask, the priority can be raised temporarily so that all tasks which share

the resource can not preempt each other.

The INTC provides the following features:



Duplicated periphery



Unique 9-bit vector per interrupt source



16 priority levels with fixed hardware arbitration within priority levels for each interrupt

source



Priority elevation for shared resource

The INTC is replicated for each processor.

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