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SPC56EL70L3 датащи(PDF) 98 Page - STMicroelectronics

номер детали SPC56EL70L3
подробное описание детали  4 KB instruction cache with error detection code
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производитель  STMICROELECTRONICS [STMicroelectronics]
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SPC56EL70L3 датащи(HTML) 98 Page - STMicroelectronics

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Electrical characteristics
SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5
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DocID023953 Rev 5
Table 25. ADC conversion characteristics
Symbol
Parameter
Conditions(1)
Min
Typ
Max
Unit
fCK
S
R
ADC Clock frequency (depends on ADC
configuration)
(The duty cycle depends on AD_CK(2)
frequency)
—3
—
60
MHz
fs
S
R
Sampling frequency
—
—
— 983.6(3) KHz
tsample
D Sample time(4)
60 MHz
383
—
—
ns
teval
D Evaluation time(5)
60 MHz
625
—
—
ns
CS(6)
D ADC input sampling capacitance
—
—
—
7.32
pF
CP1(6)
D ADC input pin capacitance 1
—
—
—
5(7)
pF
CP2(6)
D ADC input pin capacitance 2
—
—
—
0.8
pF
RSW1(6)
D Internal resistance of analog source
VREF range = 4.5 to 5.5 V
—
—
0.3
k
VREF range = 3.0 to 3.6 V
—
—
875
RAD(6)
D Internal resistance of analog source
—
—
—
825
INL
P Integral non linearity
—
–3
—
3
LSB
DNL
P Differential non linearity(8)
—–1
—
2
LSB
OFS
T Offset error
—
–6
—
6
LSB
GNE
T Gain error
—
–6
—
6
LSB
IS1WINJ
—
(single ADC channel)
C Max positive/negative injection
–3
—
3
mA
IS1WWINJ
(double ADC channel)
C Max positive/negative injection
|Vref_ad0 - Vref_ad1| <
150mV
–3.6
—
3.6
mA
SNR
T Signal-to-noise ratio
Vref = 3.3V
67
—
—
dB
SNR
T Signal-to-noise ratio
Vref = 5.0V
69
—
—
dB
THD
T Total harmonic distortion
—
-65
—
—
dB
SINAD
T Signal-to-noise and distortion
—
65
—
—
dB
ENOB
T Effective number of bits
—
10.5
—
—
bits
TUEIS1WINJ T
Total unadjusted error for IS1WINJ
(single ADC channels)
Without current injection
–6
—
6
LSB
With current injection
–8
—
8
LSB
TUEIS1WWINJ
P Total unadjusted error for IS1WWINJ
(double ADC channels)
Without current injection
–8
—
8
LSB
T
With current injection
–10
—
10
LSB
1. TJ = –40 to +150 °C, unless otherwise specified and analog input voltage from VAGND to VAREF.
2. AD_CK clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.
3. This is the maximum frequency that the analog portion of the ADC can attain. A sustained conversion at this frequency is
not possible.



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