SPC56EL70L3 datasheet(14/128 Pages) STMICROELECTRONICS

14 / 128 page

Introduction

SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5

14/128

DocID023953 Rev 5

The eDMA module provides the following features:



16 channels supporting 8-, 16-, and 32-bit value single or block transfers



Support variable sized queues and circular buffered queue



Source and destination address registers independently configured to post-increment

or stay constant



Support major and minor loop offset



Support minor and major loop done signals



DMA task initiated either by hardware requestor or by software



Each DMA task can optionally generate an interrupt at completion and retirement of the

task



Signal to indicate closure of last minor loop



Transfer control descriptors mapped inside the SRAM

The eDMA controller is replicated for each processing channel.

1.5.5

On-chip flash memory with ECC

This device includes programmable, non-volatile flash memory. The non-volatile memory

(NVM) can be used for instruction storage or data storage, or both. The flash memory

module interfaces with the system bus through a dedicated flash memory array controller. It

supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface to

flash memory. The module contains four 128-bit prefetch buffers. Prefetch buffer hits allow

no-wait responses. Buffer misses incur a 3 wait state response at 120 MHz.

The flash memory module provides the following features:



2 MB of flash memory in unique multi-partitioned hard macro



Sectorization:

–

Partition 1 (low address): 16 KB + 16 KB + 16 KB + 16 KB

–

Partition 2 (low address): 16 KB + 16 KB + 16 KB + 16 KB

–

Partition 3 (low address): 64 KB + 64 KB

–

Partition 4 (mid address): 128 KB + 128 KB

–

Partition 5 (high address): 256 KB + 256 KB

–

Partition 6 (high address): 256 KB + 256 KB

–

Partition 7 (high address): 256 KB + 256 KB



EEPROM emulation (in software) within same module but on different partition



16 KB test sector and 16 KB shadow sector for test, censorship device and user option

bits



Wait states:

–

Access time less or equal to 3 WS at 120 MHz + 4% FM (4-1-2-1 access)

–

Access time less or equal to 2 WS at 80 MHz + 4% FM



Flash memory line 128-bit wide with 8-bit ECC on 64-bit word (total 144 bits)



Accessed via a 64-bit wide bus for write and a 128-bit wide array for read operations



1-bit error correction, 2-bit error detection

1.5.6

On-chip SRAM with ECC

The SPC56XL70 SRAM provides a general-purpose single port memory.

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