SPC56EL70L3 datasheet(106/128 Pages) STMICROELECTRONICS

106 / 128 page

Electrical characteristics

SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5

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DocID023953 Rev 5

3.19.4

Reset sequence — start condition

The impact of the voltage thresholds on the starting point of the internal reset sequence are

becoming important if the voltage rails / signals ramp up with a very slow slew rate

compared to the overall reset sequence duration.

3.19.4.1

Destructive reset

Figure 18

shows the voltage threshold that determines the start of the Destructive Reset

Sequence, BIST enabled

and the start for the Destructive Reset Sequence, BIST disabled.

All internal

functional reset

sources

configured for

long reset

Sequence

starts with

internal reset

trigger

Release of

RESET(7)

cannot trigger

cannot

trigger

triggers

cannot

trigger

All internal

functional reset

sources

configured for

short reset

cannot trigger

cannot

trigger

cannot

trigger

triggers

1. Whether BIST is executed or not depends on the chip configuration data stored in the shadow sector of the NVM.

2. End of the internal reset sequence (as specified in Table 31) can only be observed by release of RESET if it is not held low

externally beyond the end of the internal sequence which would prolong the internal reset PHASE3 till RESET is released

externally.

3. The assertion of RESET can only trigger a reset sequence if the device was running (RESET released) before. RESET

does not gate a Destructive Reset Sequence, BIST enabled or a Destructive Reset Sequence, BIST disabled. However, it

can prolong these sequences if RESET is held low externally beyond the end of the internal sequence (beyond PHASE3).

4. If RESET is configured for long reset (default) and if BIST is enabled via chip configuration data stored in the shadow sector

of the NVM.

5. If RESET is configured for long reset (default) and if BIST is disabled via chip configuration data stored in the shadow

sector of the NVM.

6. If RESET is configured for short reset.

7. Internal reset sequence can only be observed by state of RESET if bidirectional RESET functionality is enabled for the

functional reset source which triggered the reset sequence.

Table 32. Reset sequence trigger — Reset sequence (continued)

Reset

Sequence

Trigger

Reset

Sequence

Start

Condition

Reset

Sequence

End

Indication

Reset Sequence

Destructive

reset

sequence,

bist

enabled(1)

Destructive

reset

sequence,

bisT

disabled(1)

External

reset

sequence

long, bIST

enabled

Functional

reset

sequence

long

Functional

reset

sequence

short

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