SPC56EL70L3 datasheet(103/128 Pages) STMICROELECTRONICS

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SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5

Electrical characteristics

127

3.19.2

Reset sequence description

The figures in this section show the internal states of the chip during the five different reset

sequences. The doted lines in the figures indicate the starting point and the end point for

which the duration is specified in Table 31. The start point and end point conditions as well

as the reset trigger mapping to the different reset sequences is specified in Section 3.19.3:

Reset sequence trigger mapping

With the beginning of DRUN mode the first instruction is fetched and executed. At this point

application execution starts and the internal reset sequence is finished.

The figures below show the internal states of the chip during the execution of the reset

sequence and the possible states of the signal pin RESET.

Note:

RESET is a bidirectional pin. The voltage level on this pin can either be driven low by an

external reset generator or by the chip internal reset circuitry. A high level on this pin can

only be generated by an external pull up resistor which is strong enough to overdrive the

weak internal pull down resistor. The rising edge on RESET in the following figures indicates

the time when the device stops driving it low. The reset sequence durations given in table

Table 31 are applicable only if the internal reset sequence is not prolonged by an external

reset generator keeping RESET asserted low beyond the last PHASE3.

Figure 13. Destructive Reset Sequence, BIST enabled

Table 31. RESET sequences

No.

Symbol

Parameter

Conditions

TReset

Unit

Min

Typ

Max(1)

1TDRB

CC Destructive Reset Sequence, BIST

enabled

2TDR

CC Destructive Reset Sequence, BIST

disabled

—

500

4200

5000

µs

3TERLB

CC External Reset Sequence Long, BIST

enabled

4TFRL

CC Functional Reset Sequence Long

—

150

400

µs

5TFRS

CC Functional Reset Sequence Short

—

µs

1. The maximum value is applicable only if the reset sequence duration is not prolonged by an extended assertion of RESET

by an external reset generator.

PHASE3

BIST

PHASE1,2

PHASE0

PHASE1,2

PHASE3

Establish IRC

and PWR

Flash init

Device

Config

Self Test

Setup

DRUN

LBIST

MBIST

Flash init

Device

Config

Application

Execution

TDRB, min < TReset < TDRB, max

Reset Sequence Start Condition

Reset Sequence Trigger

RESET_B

RESET

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