PC97338VLJ datasheet(181/221 Pages) NSC

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IRCFG3—Infrared Interface Configuration 3

This register holds the transceiver configuration data

for Low-Speed and High-Speed CEIR Modes.

FIGURE 88. Infrared Configuration Register 3

IRCFG4 – Infrared Interface Configuration 4

This register is used to configure the receiver data

path and enable the automatic selection of the config-

uration pins. After reset, the content of this register is

FIGURE 88. Infrared Configuration Register 4

They are unused when AMCFG is 0 or when

the ID/IRSL [2–0] pins are programmed as in-

puts.

Upon read, these bits return the values previ-

ously written.

Reserved.

Write 0.

B6–4 FIRC [2–0] – FIR Mode Transceiver Config-

uration.

These bits will drive the ID/IRSL [2–0] pins

when AMCFG is 1 and FIR Mode is selected.

They are unused when AMCFG is 0 or when

the ID/IRSL [2–0] pins are programmed as in-

puts.

Upon read, these bits return the values previ-

ously written.

Reserved.

Write 0.

B2–0 RCLC [2–0] – CEIR Mode Transceiver Con-

figuration, Low-Speed.

These bits will drive the ID/IRSL[2–0] pins

when AMCFG is 1 and CEIR Mode with 30

kHz–56 kHz receiver subcarrier frequency is

selected.

They are unused when AMCFG is 0 or when

the ID/IRSL[2–0] pins are programmed as in-

puts.

Upon read, these bits return the values previ-

ously written.

Reserved.

Write 0.

B6–4 RCHC [2–0] – CEIR Mode Transceiver Con-

figuration, High-Speed.

These bits will drive the ID/IRSL[2–0] pins

when AMCFG is 1 and CEIR Mode with 400

kHz–480 kHz receiver subcarrier frequency is

selected.

321

Reset

Required

RCLC(2-0)

RCHC(2-0)

Reserved

They are unused when AMCFG is 0 or when

the ID/IRSL[2–0] pins are programmed as in-

puts.

Upon read, these bits return the values previ-

ously written.

Reserved.

Write 0.

B2–0 Reserved.

Read/write 0's.

IRSL21_DS – ID/IRSL[2–1] Pins' Direction

Select.

This bit determines the direction of the

ID/IRSL[2–1] pins.

→ Pins' direction is input.

→ Pins' direction is output.

RXINV – IRRX Signal Invert.

This bit is provided to support optical transceiv-

ers with receive signals of opposite polarity

(active high instead of active low).

When set to 1, an inverter is placed on the re-

ceiver input signal path.

IRSL0_DS – ID0/IRSL0/IRRX2 Pin Direction

Select.

This bit determines the direction of the

ID0/IRSL0/IRRX2 pin.

→ Pin's direction is input.

→ Pin's direction is output.

IRRX_MD – IRRX Mode Select.

Determines whether a single input or two sep-

arate inputs are used for Low-Speed and High-

Speed IrDA modes.

→ One input is used for both SIR and

MIR/FIR.

→ Separate inputs are used for SIR and

MIR/FIR.

Table 97 shows the IRRXn pins used in the

PC97338 for the low-speed and high-speed

432

Reset

Required

RXINV

IRSL0_DS

IRRX_MD

AMCFG

IRSL21_DS

Reserved

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