PC97307 datasheet(180/218 Pages) NSC

180 / 218 page

180

The Internal Clock

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11.0 The Internal Clock

11.1 THE CLOCK SOURCE

The source of the internal clock of the part can be 24 MHz

or 48 MHz clock signals via the X1 pin, or an internal on-

chip clock multiplier fed by the 32.768 KHz crystal of the

Real-Time Clock (RTC). The clock source is determined by

bits 1,0 of the Power Management Control 2 (PMC2) regis-

ter of logical device 8. See Section 9.2.6 on page 174.

These bits are initialized by the CFG2 and CFG3 strap pins.

Toggling of the 32.768 KHz clock cannot be stopped while

VCCH is active. When the 32.768 KHz oscillator is not run-

ning, the internal circuit is blocked.

The internal on-chip clock multiplier generates 48 MHz and

24 MHz.

The Keyboard Controller (KBC) can operate at 8, 12 or 16

MHz. Selection of 8, 12 or 16 MHz for the KBC is done via

the SuperI/O KBC Configuration register at index F0h of

logical device 0. See Section 2.5.1 on page 36. 16 MHz is

not supported when the clock source is 24 MHz via the X1

pin. The KBC clock source can be changed only when the

KBC is inactive (disabled).

11.2 THE INTERNAL ON-CHIP CLOCK MULTIPLIER

Two events can trigger the internal on-chip clock multiplier.

One is power-on while VDD is active. The other is changing

the multiplier enable bit (bit 2 of the PMC2 register of logical

device 8) from 0 to 1. See Section 9.2.6 on page 174. This

bit can also disable the clock multiplier and its output clock.

Once enabled, the output clock of the clock multiplier is fro-

zen until the clock multiplier can provide an output clock that

meets all requirements; then it starts. When the power is

turned on, the part wakes up with the internal on-chip clock

multiplier enabled, provided that it is selected by the

CFG2,3 strap pins.

The 32.768 KHz and output clocks of the internal on-chip

clock multiplier operate regardless of the status of the Mas-

ter Reset (MR) signal. They can operate while MR is active.

The multiplier must have a 32.768 KHz input clock operat-

ing. Otherwise, the multiplier waits until this input clock

starts operating.

Bit 7 of the PMC2 register of logical device 8 is the Valid

Multiplier Clock status bit. When the 32.768 KHz clock tog-

gles before MR becomes active, this bit is usually set to 1

before power-up reset ends (while MR is high, if MR is high

for a few msec).

While it is stabilizing, the output clock is frozen and the sta-

tus bit is cleared to 0 to indicate a frozen clock. When the

clock multiplier becomes stable, the output clock starts tog-

gling and the status bit is set to 1. A longer time is required

to set the Valid Multiplier Clock status bit if the multiplier

waits for a stable 32.768 KHz clock.

The Valid Multiplier Clock status bit indicates when the

clock is operating. Software should poll this bit and activate

(enable) the KBC, FDC, UART1, the UART2 and infrared in-

terface (IR), and the Parallel Port according to its value.

The multiplier and its output clock do not use power when

they are disabled.

11.3 SPECIFICATIONS

• Wake-up time (from the time V

DD becomes valid and the

32.768 KHz clock is operating, until the clock becomes

stable) is a maximum of 1.5 msec.

• Tolerance (long term deviation) of the multiplier output

clock, above the 32.768 KHz tolerance, is

± 110 ppm.

Total tolerance is therefore

± (32.768 KHz clock toler-

ance + 110 ppm).

• Cycle by cycle variance is a maximum of 0.1 ns.

• Power consumption is a maximum of 5 mA.

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