DP83907 datasheet(23/70 Pages) NSC

23 / 70 page

50 Register Descriptions

51 CONFIGURATION REGISTERS

These registers are used to configure the operation of the DP83907 typically after power up These registers control the

configuration of bus interface setting options like interrupt selection IO base address and other specific modes

MODE CONFIGURATION REGISTER A

To prevent any accidental writes of this register it is ‘‘hidden’’ behind a previously unused register Register 0AH in the

DP83907’s Page 0 of registers was previously reserved on a read Now Configuration Register A can be read at that address

and can be written to by following a read to 0AH with a write to 0AH If any other DP83907 register accesses take place between

the read and the write then the write to 0AH will access the Remote Byte Count Register 0

RES

FRdWr

INT2

INT1

INT0

IOAD2

IOAD1

IOAD0

Bit

Symbol

Function

0 – 2

IOAD0 – IOAD2

IO ADDRESS

These three bits determine the base IO address of the DP83907 within the system’s

IO map The DP83907 occupies 20H bytes of the system’s address space

Bit210

0 0 0

0300H

0 0 1

Software (Note 1)

0 1 0

0240H

0 1 1

0280H

1 0 0

02C0H

1 0 1

0320H

1 1 0

0340H

1 1 1

0360H

Note 1

When 001 is selected the DP83907 will not respond to any IO Addresses but will allow 4 consecutive writes to 278H to

write these three bits of this register This sequence will only operate once after a power-on reset This mode allows the DP83907

to be configured via software without conflicting with other peripherals

3 – 5

INT0 – INT2

INTERRUPT LINE USED

Bit543

IRQ

000

001

010

011

100

101

110

111

FRdWR

FAST RDWR

When this bit is set high the DP83907 in IO mode will begin the next port fetch

before the current IORDIOWR has completed In slow ISA systems this may cause the data in the

port to be overwritten before the ISA cycle has been completed

RES

RESERVED

This bit must be set low for normal operation

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