DP83907 datasheet(56/70 Pages) NSC

56 / 70 page

60 Operation of DP83907 (Continued)

16-Bit IO Cycle with IO16 Fix

Some Chips

Technologies and VLSI Technologies PC-AT chip sets have timing requirements in 16-bit IO cycles that cannot

be achieved by the default DP83907 cycle described on the previous page When that cycle is executed with these chip sets

the system does not recognize the CHRDY signal and does not insert wait states The system executes a standard cycle and

deasserts IORD or IOW even if CHRDY is still deasserted The DP83907 recognizes if this situation has occurred asserts

CHRDY and sets a bus error bit in Configuration Register B to flag this error Thus the user can test any new system to see if this

error occurs and then take some remedial action The DP83907 supports a fix which can be selected by software by writing to

Configuration Register B

This fix is enabled by setting the IO16 bit of Configuration Register B In normal operation any time a valid address exists on

SA0-9 IO16 is generated Delaying IO16 until after the IORD or IOW can cure the problem on non-compliant machines The

theory is that the system is fooled into thinking an 8-bit peripheral is responding since IO16 is not generated for the valid

address and accepts 8-bit IO cycle timings for CHRDY It then rechecks IO16 after the IORD or IOW strobe and correctly

determines it is a 16-bit peripheral If a system did not recheck IO16 it would generate 2 8-bit cycles instead of 1 16-bit cycle

The DP83907 would interpret each 8-bit access as a 16-bit transfer and decrement it’s DMA byte count by 2 Eventually the

system would attempt to access the data transfer port when the DP83907 had finished transferring data and CHRDY would be

deasserted indefinitely To prevent misoperation this fix should only be implemented on systems that require it

ISA BUS BOOT PROM ACCESS TIMING

Boot PROM Read Bus Timing

TLF12082 – 40

This is the type of cycle used to read the boot PROM These accesses are entirely asynchronous with the DP83907 responding

when it decodes the correct address on SA0-19 and a SMRD If AEN is high the cycle will be ignored CHRDY is deasserted if

the DP83907 is not ready to respond and asserted when ready If it is ready immediately CHRDY is not deasserted The data will

be driven from MSD0-7 onto SD0-7

DP83907 датащи(PDF) 56 Page - National Semiconductor (TI)