DP83907 datasheet(22/70 Pages) NSC

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40 Functional Description (Continued)

Manchester Decoder

The decoder consists of a differential receiver and a PLL to

separate a Manchester encoded data stream into internal

clock signals and data The differential input must be exter-

nally terminated with two 39X resistors connected in series

if the standard 78X transceiver drop cable is used In thin

Ethernet applications these resistors are optional To pre-

vent noise from falsely triggering the decoder a squelch

circuit at the input rejects signals with levels less than

175 mV Signals more negative than b300 mV Data be-

comes valid typically within 6-bit times The DP83907 may

tolerate bit jitter up to 20 ns in the received data The decod-

er detects the end of a frame when no more mid-bit tran-

sitions are detected

Collision Translator

When in AUI Mode the Ethernet transceiver (DP8392 CTI)

detects a collision it generates a 10 MHz signal to the dif-

ferential collision inputs (CDg) of the DP83907 When

these inputs are detected active the DP83907 uses this

signal to back off its current transmission and reschedule

another one

In this mode the COL

led output will indicate when the

CDa lines are active during activity on the network This

means it will correctly indicate any collision on the network

but will not be lit for heartbeat or if there is no cable con-

nected

The collision differential inputs are terminated the same way

as the differential receive inputs The squelch circuitry is

also similar rejecting pulses levels less than b175 mV

AVCC Power Supply Consideration

The AVCC pin is the a5V power supply for the phase lock

loop (PLL) of the ENDEC unit Since this is an analog circuit

excessive noise on the AVCC pin can affect the perform-

ance of the PLL This noise if in the 10 KHz – 400 KHz

range can reduce the jitter performance of the ENDEC re-

sulting in missing packets or CRC errors

If the power supply noise is causing significant packet re-

ception error a low pass filter could be added to reduce the

power supply noise and hence improve the jitter perform-

ance Standard analog design techniques should be utilized

when laying out the power supply traces on the board If the

digital power supply is used it may be desirable to add a

one pole RC filter (designed to have a cut-off frequency of

1 KHz) as shown in

Figure 22 to improve the jitter perform-

ance The AVCC draws 3 mA–4 mA so the voltage across

the resister is less than 90 mV which will not affect the

PLL’s operation

TLF12082 – 17

FIGURE 22 Filtering Power Supply Noise

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