DP83907 datasheet(24/70 Pages) NSC

24 / 70 page

50 Register Descriptions (Continued)

MODE CONFIGURATION REGISTER B

To prevent any accidental writes of this register it is ‘‘hidden’’ behind a previously unused register Register 0BH in the

DP83907’s Page 0 of registers was previously reserved on a read Now Configuration Register B can be read at that address

and can be written to by following a read to 0BH with a write to 0BH If any other DP83907 register accesses take place between

the read and the write then the write to 0BH will access the Remote Byte Count Register 1 Care should be taken when

writing to this register as GDLINK and BE are not simple readwrite bits

eg the user can not change the physical layer by

reading B or-ing the returned value with the bits to be set and writing this value to B This could inadvertently disable link

integrity generation and clear a bus error indication before it was noted

EELOAD

BPWR

RES

IO16CON

GDLINK

PHYS1

PHYS0

Bit

Symbol

Function

0 – 1

PHYS0 –

PHYSICAL LAYER INTERFACE

These 2 bits determine which type of physical interface the DP83907 is

using The 2 TPI interfaces use twisted pair outputs and inputs while the other 2 interfaces use the AUI

PHYS1

outputs and inputs In 10BASE5 mode the THICKTHIN output pin is driven low in 10BASE2 mode it is

driven high This can be used to enable the DC-DC converter required by the 10BASE2 specification to

provide electrical isolation The Non spec TPI mode is a twisted pair mode with reduced receive squelch

levels This allows the use of longer cable lengths than specified in the twisted pair specification or the use

of cable with higher losses

Bit10

0 0

TPI (10BASE-T Compatible Squelch Level)

0 1

Thin Ethernet (10BASE2)

1 0

Thick Ethernet (10BASE5) (AUI Port)

1 1

TPI (Reduced Squelch Level)

GDLINK

GOOD LINK

Whena1is written to this bit the link test pulse generation and integrity checking is disabled

When this bit is read it will indicate the link status reflecting the value shown on the LED output It is 0 if the

DP83907 is in AUI mode or if link testing is enabled and the link integrity is bad (ie the twisted pair link has

been broken) It is 1 if the DP83907 is in TPI mode link integrity checking is enabled and the link integrity is

good (ie the twisted pair link has not been broken) or if the link testing is disabled

IO16CON

IO16 CONTROL

When this bit is set high the DP83907 generates IO16 after IORD or IOWR go active If

low this output is generated only on address decode

RES

RESERVED

This bit must be set low for normal operation

5BE

BUS ERROR

This bit shows that the DP83907 has detected a bus error condition This will go high if the

DP83907 attempts to insert wait states into a system access and the system terminates the cycle without

inserting the wait states Writing a one to this bit clears it to zero Writing a zero has no effect

BPWR

BOOT PROM WRITE

When this bit is low no write cycles are generated to the boot PROM

EELOAD

EEPROM LOAD

Writinga1to this bit enables the EEPROM load algorithm as detailed in Section 4 This

bit should not be configured to be high either from switches or an EEPROM

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