DP83907 datasheet(46/70 Pages) NSC

46 / 70 page

60 Operation of DP83907 (Continued)

Error Recovery

If the packet is rejected as shown the DMA is restored by

the DP83907 by reprogramming the DMA starting address

pointed to by the Current Page Register

Storage Format for Received Packets

The following diagrams describe the format for how re-

ceived packets are placed into memory by the local DMA

channel These modes are selected in the Data Configura-

tion Register

AD15

AD8

AD7

AD0

Next Packet Pointer

Receive Status

Receive Byte Count 1

Receive Byte Count 0

Byte 2

Byte 1

BOS e 0 WTS e 1 in Data Configuration Register This format is used with

Series 32xxx or 808xx processors

AD15

AD8

AD7

AD0

Next Packet Pointer

Receive Status

Receive Byte Count 0

Receive Byte Count 1

Byte 1

Byte 2

BOS e 1 WTS e 1 in Data Configuration Register This format is used with

680 x 0 type processors (Note the Receive Count ordering remains the

same for BOS e 0or1 )

Receive Status

Next Packet Pointer

Receive Byte Count 0

Receive Byte Count 1

Byte 0

Byte 1

BOS e 0 WTS e 0 in Data Configuration Register This format is used with

general 8-bit processors

64 PACKET TRANSMISSION

The Local DMA is also used during transmission of a pack-

et Three registers control the DMA transfer during trans-

mission a Transmit Page Start Address Register (TPSR)

and the Transmit Byte Count Registers (TBCR0 1) When

the DP83907 receives a command to transmit the packet

pointed to by these registers buffer memory data will be

moved into the FIFO as required during transmission The

DP83907 will generate and append the preamble synch

and CRC fields

General Transmit Packet Format

Transmit

Destination Address

6 Bytes

Byte

Source Address

6 Bytes

Count

TypeLength

2 Bytes

TBCR0 1

Data

46 Bytes

Pad (if data k 46 Bytes)

Transmit Packet Assembly

The DP83907 requires a contiguous assembled packet with

the format shown The transmit byte count includes the

Destination Address Source Address Length Field and

Data It does not include preamble and CRC When trans-

mitting data smaller than 46 bytes the packet must be pad-

ded to a minimum size of 64 bytes The programmer is re-

sponsible for adding and stripping pad bytes

The packets are placed in the buffer RAM by the system In

IO Mode the system programs the NIC Core’s Remote

DMA to mode the data from the data port to the RAM hand-

shaking with system transfers loading the IO data port In

Shared Memory Mode the packets are written directly to the

RAM by system using standard memory transfer instruc-

tions (MOV)

For IO mode the data transfer must be 16 bits (1 word)

when in 16 bit mode and 8 bits when the DP83907 is set in

8 bit mode The data width is selected by setting the WTS

bit in the Data Configuration Register and setting the DWID

pin for the proper mode

In Shared Memory mode data transfer can be accomplished

by using either 8- or 16-bit data transfer instructions be-

cause this mode responds to 816 bit data signaling on the

ISA bus In this mode Shared Memory Control Register 2 bit

6 sets the bus interface data width and the NIC Core’s data

width is set by the WTS bit in the Data Configuration Regis-

ter

Transmission

Prior to transmission the TPSR (Transmit Page Start Regis-

ter) and TBCR0 TBCR1 (Transmit Byte Count Registers)

must be initialized To initiate transmission of the packet the

TXP bit in the Command Register is set The Transmit

Status Register (TSR) is cleared and the DP83907 begins to

prefetch transmit data from memory (unless the DP83907 is

currently receiving) If the interframe gap has timed out the

DP83907 will begin transmission

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