DP83907 datasheet(25/70 Pages) NSC

25 / 70 page

50 Register Descriptions (Continued)

HARDWARE CONFIGURATION REGISTER C

This register is configured during a RESET and can be accessed by 3rd consecutive read config register A

3210

SOFEN

RES

BPS3

BPS2

BPS1

BPS0

Bit

Symbol

Function

0–3

BPS0–3

BOOT PROM SELECT

Selects address at which boot PROM begins and the size When the system reads

within the selected memory area DP83907 reads the data in through MSD0 – 7 and drives it onto the system

data bus The following are valid addresses and sizes

Bit 3

Bit 2

Bit 1

Bit 0

Address

Size

No Boot PROM

0C000H

0C400H

0C800H

0CC00H

0D000H

0D400H

0D800H

0DC00H

0C000H

32K

0C800H

32K

0D000H

32K

0D800H

32K

0C000H

64K

0D000H

64K

RES

RESERVED

This bit must be set low for normal operation

RES

RESERVED

This bit must be set high for normal operation

RES

RESERVED

This bit must be set low for normal operation

SOFEN

SOFTWARE ENABLE

If this bit is set low then the user can program configuration registers A and B in

software If this bit is set high then the configuration registers are not accessible If EECONFIG is high the

configuration from the switches will be overwritten by the configuration from the EEPROM even if this bit is

pulled high

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