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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DP83907 датащи(PDF) 59 Page - National Semiconductor (TI) |
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DP83907 датащи(HTML) 59 Page - National Semiconductor (TI) |
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59 / 70 page  70 In-Circuit Test (ICT) Description The test register is made available only when the test bit (D7 of cnfg A) is set at the following IO address IO mode Base a 1FHex The test register contains the following bits Note that when the test bit is low the test register is held set except for D4 and D0 which is reset TABLE I Test Modes (test pin e 1) Test Mode D7 D6 D5 D4 D3 D2 D1 D0 SAk9l 1VIH VIL 11111110 X 2VOH VOL 11101010 1 VIL VIH test mode when high will AND all inputs (except RESET pin) and present outcome on IRQk3l To enable this st-nic mode must NOT be entered VOH VOL test mode is active in st-nic mode if SAk9le1 Then all op’s switch with SAk4l as per Table 2 VOH VOL mode output states (SAk9le1) TABLE II Output SAk4le0SAk4le1 MSAk131l 1555 Hex 0AAA Hex MSDk150l AAAA Hex 5555 Hex SDk150l AAAA Hex 5555 Hex IRQk15 12 11 10 9 5 4 3l A2 Hex 5D Hex MSWR 01 MSRD 10 RCS 01 BPCS 01 EECS 1 0 IO16 00 CHRDY (AEN AORD Must be Low) 0 0 GDLNK ACT COL 0 1 0 1 0 1 THIN 1 0 59 |
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